Inventor

ANDERS MARK A

US50 patents

⚠️ This page may combine multiple inventors who share the name “ANDERS MARK A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ANDERS MARK A

INTEL CORP

Instructions and logic to perform floating point and integer operations for machine learning

Instructions and logic to perform floating-point and integer operations for machine learning

Instructions and logic to perform floating point and integer operations for machine learning

Instructions and logic to perform floating-point and integer operations for machine learning

Instructions and logic to perform floating-point and integer operations for machine learning

Variable precision floating point multiply-add circuit

Full-swing source-follower leakage tolerant dynamic logic

Encoder and decoder circuits for dynamic bus

Low loss interconnect structure for use in microelectronic circuits

Single ended domino compatible dual function generator circuits

Sparse tree adder circuit

Spatially divided circuit-switched channels for a network-on-chip

Method, apparatus and system for a source-synchronous circuit-switched network on a chip (NOC)

Reconfigurable SIMD vector processing system

Voltage-level converter

Hierarchical clock grid for on-die salphasic clocking

Low switching activity dynamic driver for high performance interconnects

Apparatus and method for an address generation circuit

Combined guaranteed throughput and best effort network-on-chip

Instructions and logic to perform floating point and integer operations for machine learning

Variable format, variable sparsity matrix multiplication instruction

Parallel direction decode circuits for network-on-chip

Link delay based routing apparatus for a network-on-chip

Systems, apparatuses, and methods for K nearest neighbor search

Instructions and logic to perform floating point and integer operations for machine learning

Instructions and logic to perform floating point and integer operations for machine learning

Instructions and logic to perform floating point and integer operations for machine learning

Low loss interconnect structure for use in microelectronic circuits

Single ended current-sensed bus with novel static power free receiver circuit

Clock receiver circuit for on-die salphasic clocking

Clock receiver circuit for on-die salphasic clocking

High bandwidth core to network-on-chip interface

High bandwidth core to network-on-chip interface

Adder circuit with sense-amplifier multiplexer front-end

Low-swing bus driver and receiver

Reconfigurable interconnect structure in integrated circuits

Motion estimation for video processing

Pipelined hybrid packet/circuit-switched network-on-chip

Pointer chasing across distributed memory

System for multicast and reduction communications on a network-on-chip

Edge-aware synchronization of a data signal

Scalable crossbar apparatus and method for arranging crossbar circuits

Transition-encoder sense amplifier

Adaptively switched network-on-chip

Data converter and a delay threshold comparator

Systems, apparatuses, and methods for K nearest neighbor search

MARVELL INT LTD

Distributed ring control circuits for Viterbi traceback

Distributed ring control circuits for Viterbi traceback

ANDERS MARK A

Architecture and method for hybrid circuit-switched and packet-switched router

MATHEW SANU K

Instruction and logic for a simon block cipher