Inventor

SHPEISMAN TATIANA

US77 patents

⚠️ This page may combine multiple inventors who share the name “SHPEISMAN TATIANA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHPEISMAN TATIANA

INTEL CORP

Compute unit having independent data paths

Mixed inference using low and high precision

Instructions and logic to perform floating point and integer operations for machine learning

Instructions and logic to perform floating-point and integer operations for machine learning

Instructions and logic to perform floating point and integer operations for machine learning

Instructions and logic to perform floating-point and integer operations for machine learning

Instructions having support for floating point and integer data types in the same register

Instructions and logic to perform floating-point and integer operations for machine learning

Thread synchronization methods and apparatus for managed run-time environments

Method for fast exception handling

Method and system of controlling dynamically compiled native code size

Specialized fixed function hardware for efficient convolution

Person tracking and privacy and acceleration of data using autonomous machines

Compute optimization mechanism

Function callback mechanism between a central processing unit (CPU) and an auxiliary processor

Efficient non-transactional write barriers for strong atomicity

Method and apparatus for performing dynamic optimization for software transactional memory

Thread synchronization with lock inflation methods and apparatus for managed run-time environments

Methods and apparatus for optimizing the operating speed and size of a computer program

Method for implementing dynamic type checking

Adaptive scheduling for task assignment among heterogeneous processor cores

Safe code-motion of dangerous instructions during compiler optimization

Concurrent multi-datatype execution within a processing resource

Convolutional neural network optimization mechanism

Method for providing garbage collection support

Instructions and logic to perform floating point and integer operations for machine learning

Specialized fixed function hardware for efficient convolution

Graphics processing integrated circuit package

Hybrid graphics processor-field programmable gate array system

Compute optimization mechanism

Dynamic precision for neural network compute operations

Graphics processing integrated circuit package

Function callback mechanism between a Central Processing Unit (CPU) and an auxiliary processor

Enabling maximum concurrency in a hybrid transactional memory system

Work stealing in heterogeneous computing systems

Dynamic precision for neural network compute operations

Instructions and logic to perform floating point and integer operations for machine learning

Compute optimization mechanism

Instructions and logic to perform floating point and integer operations for machine learning

Dynamic precision for neural network compute operations

Instructions and logic to perform floating point and integer operations for machine learning

Compute optimization mechanism

Compute optimization mechanism

Transactional memory management techniques

XEROX CORP

Tools for efficient sparse matrix computation

Ordered sparse accumulator and its use in efficient sparse matrix computation

NI YANG

Method and apparatus to facilitate shared pointers in a heterogeneous platform

SHPEISMAN TATIANA

Dynamic optimization for removal of strong atomicity barriers

SAHA BRATIN

Mechanisms for strong atomicity in a transactional memory system

GOTTSCHLICH JUSTIN E

Unbounded transactional memory with forward progress guarantees using a hardware global lock