Inventor
RAZA S BABAR
US50 patents
⚠️ This page may combine multiple inventors who share the name “RAZA S BABAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CYPRESS SEMICONDUCTOR CORP
49 patentsUS6917661B1Jul 12, 2005
Method, architecture and circuitry for controlling pulse width in a phase and/or frequency detector
CYPRESS SEMICONDUCTOR CORP58 citations96
US7738496B1Jun 15, 2010
Device that provides the functionality of dual-ported memory using single-ported memory for multiple clock domains
CYPRESS SEMICONDUCTOR CORP39 citations93
US7016349B1Mar 21, 2006
Logic for generating multicast/unicast address (es)
CYPRESS SEMICONDUCTOR CORP21 citations93
US6816955B1Nov 9, 2004
Logic for providing arbitration for synchronous dual-port memory
CYPRESS SEMICONDUCTOR CORP28 citations93
US6640267B1Oct 28, 2003
Architecture for multi-queue storage element
CYPRESS SEMICONDUCTOR CORP32 citations93
US5986489ANov 16, 1999
Slew rate control circuit for an integrated circuit
CYPRESS SEMICONDUCTOR CORP35 citations93
US5943488AAug 24, 1999
Method and apparatus to generate mask programmable device
CYPRESS SEMICONDUCTOR CORP38 citations93
US5926035AJul 20, 1999
Method and apparatus to generate mask programmable device
CYPRESS SEMICONDUCTOR CORP32 citations93
US7382805B1Jun 3, 2008
Method and apparatus for aggregating Ethernet streams
CYPRESS SEMICONDUCTOR CORP31 citations92
US7184359B1Feb 27, 2007
System and method for staging concurrent accesses to a memory address location via a single port using a high speed sampling clock
CYPRESS SEMICONDUCTOR CORP36 citations92
US6510487B1Jan 21, 2003
Design architecture for a parallel and serial programming interface
CYPRESS SEMICONDUCTOR CORP25 citations91
US6195360B1Feb 27, 2001
Architecture for a dual segment dual speed repeater
CYPRESS SEMICONDUCTOR CORP21 citations91
US6816979B1Nov 9, 2004
Configurable fast clock detection logic with programmable resolution
CYPRESS SEMICONDUCTOR CORP19 citations88
US7934057B1Apr 26, 2011
Logic for implementing a dual clock domain read access with predictable timing for bi-directional inputs/outputs
CYPRESS SEMICONDUCTOR CORP14 citations84
US6925506B1Aug 2, 2005
Architecture for implementing virtual multiqueue fifos
CYPRESS SEMICONDUCTOR CORP13 citations84
US6631455B1Oct 7, 2003
Logic for initializing the depth of the queue pointer memory
CYPRESS SEMICONDUCTOR CORP14 citations84
US5745354AApr 28, 1998
Pump circuit for generating multiple high voltage outputs from two different inputs
CYPRESS SEMICONDUCTOR CORP17 citations84
US6657472B1Dec 2, 2003
Circuit, system, and method for programmably setting an input to a prioritizer of a latch to avoid a non-desired output state of the latch
CYPRESS SEMICONDUCTOR CORP18 citations83
US6810098B1Oct 26, 2004
FIFO read interface protocol
CYPRESS SEMICONDUCTOR CORP8 citations74
US6715021B1Mar 30, 2004
Out-of-band look-ahead arbitration method and/or architecture
CYPRESS SEMICONDUCTOR CORP8 citations74
US6629226B1Sep 30, 2003
Fifo read interface protocol
CYPRESS SEMICONDUCTOR CORP8 citations74
US6603771B1Aug 5, 2003
Highly scalable architecture for implementing switch fabrics with quality of services
CYPRESS SEMICONDUCTOR CORP11 citations74
US6584517B1Jun 24, 2003
Circuit and method for supporting multicast/broadcast operations in multi-queue storage devices
CYPRESS SEMICONDUCTOR CORP11 citations74
US6578118B1Jun 10, 2003
Method and logic for storing and extracting in-band multicast port information stored along with the data in a single memory without memory read cycle overhead
CYPRESS SEMICONDUCTOR CORP12 citations74
US6502197B1Dec 31, 2002
Method and architecture for synchronizing a transport and path overhead generator and/or extractor to an path overhead transport and path processor
CYPRESS SEMICONDUCTOR CORP12 citations74
US6118299ASep 12, 2000
Method and apparatus to generate mask programmable device
CYPRESS SEMICONDUCTOR CORP10 citations74
US5973545AOct 26, 1999
Single pump circuit for generating high voltage from two different inputs
CYPRESS SEMICONDUCTOR CORP11 citations74
US5748559AMay 5, 1998
Circuit for high speed serial programming of programmable logic devices
CYPRESS SEMICONDUCTOR CORP15 citations74
US5654652AAug 5, 1997
High-speed ratio CMOS logic structure with static and dynamic pullups and/or pulldowns using feedback
CYPRESS SEMICONDUCTOR CORP10 citations74
US5565791AOct 15, 1996
Method and apparatus for disabling unused sense amplifiers
CYPRESS SEMICONDUCTOR CORP8 citations74
US5345112ASep 6, 1994
Integrated circuit with programmable speed/power adjustment
CYPRESS SEMICONDUCTOR CORP17 citations74
US6243664B1Jun 5, 2001
Methods for maximizing routability in a programmable interconnect matrix having less than full connectability
CYPRESS SEMICONDUCTOR CORP7 citations73
US5923868AJul 13, 1999
Methods for maximizing routability in a programmable interconnect matrix having less than full connectability
CYPRESS SEMICONDUCTOR CORP5 citations73
US5848066ADec 8, 1998
Methods for maximizing routability in a programmable interconnect matrix having less than full connectability
CYPRESS SEMICONDUCTOR CORP7 citations73
US5821794AOct 13, 1998
Clock distribution architecture and method for high speed CPLDs
CYPRESS SEMICONDUCTOR CORP11 citations73
US5689686ANov 18, 1997
Methods for maximizing routability in a programmable interconnect matrix having less than full connectability
CYPRESS SEMICONDUCTOR CORP8 citations73
US6055241AApr 25, 2000
Architecture for a dual segment dual speed repeater
CYPRESS SEMICONDUCTOR CORP10 citations72
US5635856AJun 3, 1997
High speed programmable macrocell with combined path for storage and combinatorial modes
CYPRESS SEMICONDUCTOR CORP15 citations71
US6665265B1Dec 16, 2003
Overhead serial communication scheme
CYPRESS SEMICONDUCTOR CORP4 citations63
US6640300B1Oct 28, 2003
Method and apparatus for width and depth expansion in a multi-queue system
CYPRESS SEMICONDUCTOR CORP6 citations63
US6628656B1Sep 30, 2003
Circuit, method and/or architecture for improving the performance of a serial communication link
CYPRESS SEMICONDUCTOR CORP2 citations63
US6625177B1Sep 23, 2003
Circuit, method and/or architecture for improving the performance of a serial communication link
CYPRESS SEMICONDUCTOR CORP3 citations63
US6625711B1Sep 23, 2003
Method and/or architecture for implementing queue expansion in multiqueue devices
CYPRESS SEMICONDUCTOR CORP5 citations63
US6581144B1Jun 17, 2003
Method and logic for initializing the forward-pointer memory during normal operation of the device as a background process
CYPRESS SEMICONDUCTOR CORP5 citations63
US6229811B1May 8, 2001
Architecture for a dual segment dual speed repeater
CYPRESS SEMICONDUCTOR CORP4 citations61
US6115364ASep 5, 2000
Distributed port select method for a multi-segment repeater
CYPRESS SEMICONDUCTOR CORP2 citations61
US6097738AAug 1, 2000
Multi-speed retainer
CYPRESS SEMICONDUCTOR CORP3 citations61
US7343510B1Mar 11, 2008
Method and device for selecting one of multiple clock signals based on frequency differences of such clock signals
CYPRESS SEMICONDUCTOR CORP4 citations59
US7334147B1Feb 19, 2008
Method and architecture for synchronizing a path generator and/or extractor to a processor
CYPRESS SEMICONDUCTOR CORP0 citations52