Inventor

KRISHNAN SRINATH

US51 patents

⚠️ This page may combine multiple inventors who share the name “KRISHNAN SRINATH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KRISHNAN SRINATH

ADVANCED MICRO DEVICES INC

Method for increasing gate capacitance by using both high and low dielectric gate material

Fast Mosfet with low-doped source/drain

Field effect transistor with self alligned double gate and method of forming same

SOI MOSFET and method of fabrication

Self-aligned floating body control for SOI device through leakage enhanced buried oxide

Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile

Method of growing as a channel region to reduce source/drain junction capacitance

Method for fabricating a MOSFET device structure which facilitates mitigation of junction capacitance and floating body effects

Semiconductor device having enhanced gate capacitance by using both high and low dielectric materials

SOI device with structure for enhancing carrier recombination and method of fabricating same

Suppression of boron segregation for shallow source and drain junctions in semiconductors

SOI MOSFET having amorphized source drain and method of fabrication

Multi-Thickness silicide device formed by succesive spacers

Argon implantation after silicidation for improved floating-body effects

Circuit technique to deal with floating body effects

Semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions

Method of making a multi-thickness silicide SOI device

Method of fabricating semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions

Formation of low thermal budget shallow abrupt junctions for semiconductor devices

Fast MOSFET with low-doped source/drain

Dual purpose test structure for gate-body current measurement in PD/SOI and for direct extraction of physical gate length in scaled CMOS technologies

Method of making a test structure for gate-body current and direct extraction of physical gate length using conventional CMOS

Silicon-on-insulator (SOI)electrostatic discharge (ESD) protection device with backside contact plug

Selectively thin silicon film for creating fully and partially depleted SOI on same wafer

Silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device with backside contact opening

Removable spacer technology using ion implantation to augment etch rate differences of spacer materials

Capacitively coupled DTMOS on SOI

Method of fabricating transistors with low thermal budget

Body-tied-to-body SOI CMOS inverter circuit

Shallow trench isolation process utilizing differential liners

Method of fabricating multi-thickness silicide device formed by disposable spacers

SOI device with source/drain extensions and adjacent shallow pockets

MOS-type transistor processing utilizing UV-nitride removable spacer and HF etch

SOI device with structure for enhancing carrier recombination and method of fabricating same

Body-tied-to-body SOI CMOS inverter circuit

Tip architecture with SPE for buffer and deep source/drain regions

Method of making a hybrid SOI device that suppresses floating body effects

Structure, and a method of realizing, for efficient heat removal on SOI

Field effect transistor with a buried and confined metal plate to control short channel effects

Capacitively coupled DTMOS on SOI for multiple devices

Method of creating selectively thin silicon/oxide for making fully and partially depleted SOI on same waffer

Device and method for testing performance of silicon structures

Semiconductor device with a silicon-on-void structure and method of making the same

Shallow trench isolation process utilizing differential liners

Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure

Method of improving MOS device performance by controlling degree of depletion in the gate electrode

Dual SOI film thickness for body resistance control

Method for making accumulation mode N-channel SOI

Shallow trench isolation process utilizing differential liners

SAP SE

Maintaining data integrity during data migration