Inventor

NOBLE JR WENDELL P

US25 patents

⚠️ This page may combine multiple inventors who share the name “NOBLE JR WENDELL P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NOBLE JR WENDELL P

IBM

MOSFET with raised STI isolation self-aligned to the gate stack

Electrically alterable double dense memory

Method of fabricating a gate connector

Trench capacitor field shield with sidewall contact

Method for fabricating a MOSFET with raised STI isolation self-aligned to the gate stack

Method for providing silicide bridge contact between silicon regions separated by a thin dielectric

Process for building borderless bitline, wordline and DRAM structure and resulting structure

Five square folded-bitline DRAM cell

Method of making self-aligned recessed oxide isolation regions

Borderless wordline for DRAM cell

Process for building borderless bitline, wordline amd DRAM structure

Method for reducing parasitic capacitance in integrated circuit structures

Borderless bitline and wordline DRAM structure

Method for making borderless wordline for DRAM cell

Process for making a small dynamic memory cell structure

MICRON TECHNOLOGY INC

High density SRAM cell with latched vertical transistors

High density planar SRAM cell using bipolar latch-up and gated diode breakdown

High density vertical SRAM cell using bipolar latchup induced by gated diode breakdown

High density planar SRAM cell with merged transistors

Method of fabricating a transistor on a substrate to operate as a fully depleted structure

High density planar SRAM cell using bipolar latch-up and gated diode breakdown

High density vertical SRAM cell using bipolar latchup induced by gated diode breakdown

High density SRAM cell with latched vertical transistors

High density SRAM cell with latched vertical transistors

(unassigned)

Method of making a trench capacitor field shield with sidewall contact