Inventor

JOYNER JODY BERN

US28 patents

Patents

28 patents

US6848003B1Jan 25, 2005

Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response

IBM87 citations98

US6591321B1Jul 8, 2003

Multiprocessor system bus protocol with group addresses, responses, and priorities

IBM89 citations98

US6910062B2Jun 21, 2005

Method and apparatus for transmitting packets within a symmetric multiprocessor system

IBM19 citations93

US6591307B1Jul 8, 2003

Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response

IBM25 citations93

US7308558B2Dec 11, 2007

Multiprocessor data processing system having scalable data interconnect and data routing mechanism

IBM39 citations92

US6865695B2Mar 8, 2005

Robust system bus recovery

IBM20 citations92

US6748493B1Jun 8, 2004

Method and apparatus for managing memory operations in a data processing system using a store buffer

IBM41 citations92

US6360297B1Mar 19, 2002

System bus read address operations with data ordering preference hint bits for vertical caches

IBM31 citations92

US7502917B2Mar 10, 2009

High speed memory cloning facility via a lockless multiprocessor mechanism

IBM11 citations84

US7069394B2Jun 27, 2006

Dynamic data routing mechanism for a high speed memory cloner

IBM18 citations84

US6898677B2May 24, 2005

Dynamic software accessibility to a microprocessor system with a high speed memory cloner

IBM17 citations84

US6519665B1Feb 11, 2003

Multi-node data processing system and communication protocol in which a stomp signal is propagated to cancel a prior request

IBM15 citations84

US6519649B1Feb 11, 2003

Multi-node data processing system and communication protocol having a partial combined response

IBM15 citations84

US7308536B2Dec 11, 2007

System bus read data transfers with data ordering control bits

IBM6 citations74

US6671712B1Dec 30, 2003

Multi-node data processing system having a non-hierarchical interconnect architecture

IBM8 citations74

US6535957B1Mar 18, 2003

System bus read data transfers with bus utilization based data ordering

IBM9 citations74

US6532519B2Mar 11, 2003

Apparatus for associating cache memories with processors within a multiprocessor data processing system

IBM12 citations74

US6493814B2Dec 10, 2002

Reducing resource collisions associated with memory units in a multi-level hierarchy memory system

IBM8 citations74

US6349360B1Feb 19, 2002

System bus read address operations with data ordering preference hint bits

IBM8 citations74

US6915390B2Jul 5, 2005

High speed memory cloning facility via a coherently done mechanism

IBM7 citations73

US7526631B2Apr 28, 2009

Data processing system with backplane and processor books configurable to support both technical and commercial workloads

IBM6 citations63

US7007128B2Feb 28, 2006

Multiprocessor data processing system having a data routing mechanism regulated through control communication

IBM3 citations63

US6874063B1Mar 29, 2005

JOYNER JODY BERN

Patents

Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response

Multiprocessor system bus protocol with group addresses, responses, and priorities

Method and apparatus for transmitting packets within a symmetric multiprocessor system

Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response

Multiprocessor data processing system having scalable data interconnect and data routing mechanism

Robust system bus recovery

Method and apparatus for managing memory operations in a data processing system using a store buffer

System bus read address operations with data ordering preference hint bits for vertical caches

High speed memory cloning facility via a lockless multiprocessor mechanism

Dynamic data routing mechanism for a high speed memory cloner

Dynamic software accessibility to a microprocessor system with a high speed memory cloner

Multi-node data processing system and communication protocol in which a stomp signal is propagated to cancel a prior request

Multi-node data processing system and communication protocol having a partial combined response

System bus read data transfers with data ordering control bits

Multi-node data processing system having a non-hierarchical interconnect architecture

System bus read data transfers with bus utilization based data ordering

Apparatus for associating cache memories with processors within a multiprocessor data processing system

Reducing resource collisions associated with memory units in a multi-level hierarchy memory system

System bus read address operations with data ordering preference hint bits

High speed memory cloning facility via a coherently done mechanism

Data processing system with backplane and processor books configurable to support both technical and commercial workloads

Multiprocessor data processing system having a data routing mechanism regulated through control communication

System bus read data transfers with data ordering control bits

High speed memory cloner within a data processing system

High speed memory cloner with extended cache coherency protocols and responses

High speed memory cloning facility via a source/destination switching mechanism

Imprecise cache line protection mechanism during a memory clone operation

Data processing system with naked cache line write operations