Inventor

HOHAGE JOERG

DE32 patents

⚠️ This page may combine multiple inventors who share the name “HOHAGE JOERG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOHAGE JOERG

ADVANCED MICRO DEVICES INC

Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device

Technique for creating different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified intrinsic stress

Barrier layer for a copper metallization layer including a low-k dielectric

Semiconductor device with a copper line having an increased resistance against electromigration and a method of forming the same

Method of forming capped copper interconnects with reduced hillocks

Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device

Etch stop layer for a metallization layer with enhanced adhesion, etch selectivity and hermeticity

Method of forming a field effect transistor comprising a stressed channel region

Method of forming copper interconnect capping layers with improved interface and adhesion

Nitrogen-enriched low-k barrier layer for a copper metallization layer

Method of forming an insulating capping layer for a copper metallization layer by using a silane reaction

Etch stop layer for a metallization layer with enhanced etch selectivity and hermeticity

Method of forming a field effect transistor having a stressed channel region

Surface treatment and capping layer process for producing a copper interface in a semiconductor device

Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device

Arc layer having a reduced flaking tendency and a method of manufacturing the same

Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectric

Interlayer dielectric material in a semiconductor device comprising a doublet structure of stressed materials

Stress transfer by sequentially providing a highly stressed etch stop material and an interlayer dielectric in a contact layer stack of a semiconductor device

Interlayer dielectric material in a semiconductor device comprising stressed layers with an intermediate buffer material

Method of forming an insulating capping layer for a copper metallization layer

Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region

Technique for creating different mechanical strain in different CPU regions by forming an etch stop layer having differently modified intrinsic stress

HOHAGE JOERG

Interlayer dielectric material in a semiconductor device comprising stressed layers with an intermediate buffer material

Method of forming a dielectric cap layer for a copper metallization by using a hydrogen based thermal-chemical treatment

Compressive stress transfer in an interlayer dielectric of a semiconductor device by providing a bi-layer of superior adhesion and internal stress

GLOBALFOUNDRIES INC

Reduced wafer warpage in semiconductors by stress engineering in the metallization system

FROHBERG KAI

Stress engineering in a contact level of semiconductor devices by stressed conductive layers and an isolation spacer

AUBEL OLIVER

Providing superior electromigration performance and reducing deterioration of sensitive low-k dielectrics in metallization systems of semiconductor devices

LEHR MATTHIAS

Protection of reactive metal surfaces of semiconductor devices during shipping by providing an additional protection layer

RICHTER RALF

Non-insulating stressed material layers in a contact level of semiconductor devices

LETZ TOBIAS

Technique for forming a passivation layer without a terminal metal