Inventor

RUELKE HARTMUT

DE34 patents

⚠️ This page may combine multiple inventors who share the name “RUELKE HARTMUT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RUELKE HARTMUT

ADVANCED MICRO DEVICES INC

Methods of forming capped copper interconnects with improved electromigration resistance

Method of forming capped copper interconnects with reduced hillock formation and improved electromigration resistance

Barrier layer for a copper metallization layer including a low-k dielectric

Semiconductor device with a copper line having an increased resistance against electromigration and a method of forming the same

Copper damascene with low-k capping layer and improved electromigration reliability

Method of forming capped copper interconnects with reduced hillocks

Method of forming a field effect transistor comprising a stressed channel region

Method of forming copper interconnect capping layers with improved interface and adhesion

Method of forming a substrate contact in a field effect transistor formed over a buried insulator layer

Nitrogen-enriched low-k barrier layer for a copper metallization layer

Process for forming PECVD undoped oxide with a super low deposition rate on a single state deposition

Copper damascene with low-k capping layer and improved electromigration reliability

Process for forming PECVD nitride with a very low deposition rate

Low-k dielectric layer stack including an etch indicator layer for use in the dual damascene technique

Method of forming silicon oxynitride films

Method of forming a field effect transistor having a stressed channel region

Surface treatment and capping layer process for producing a copper interface in a semiconductor device

Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectric

Nitrogen-free ARC/capping layer and method of manufacturing the same

Nitrogen-free ARC layer and a method of manufacturing the same

Dielectric barrier layer for a copper metallization layer having a varying silicon concentration along its thickness

RUELKE HARTMUT

Technique for forming a dielectric interlayer above a structure including closely spaced lines

Spacer for a gate electrode having tensile stress and a method of forming the same

Enhanced adhesion of PECVD carbon on dielectric materials by providing an adhesion interface

GLOBALFOUNDRIES INC

Particle reduction in PECVD processes for depositing low-k material by using a plasma assisted post-deposition step

Spacer for a gate electrode having tensile stress and a method of forming the same

Method of forming a TEOS cap layer at low temperature and reduced deposition rate

HOHAGE JOERG

Method of forming a dielectric cap layer for a copper metallization by using a hydrogen based thermal-chemical treatment

Compressive stress transfer in an interlayer dielectric of a semiconductor device by providing a bi-layer of superior adhesion and internal stress

HUY KATJA

Method of improving the wafer-to-wafer thickness uniformity of silicon nitride layers

FROHBERG KAI

Stress engineering in a contact level of semiconductor devices by stressed conductive layers and an isolation spacer

MAYER ULRICH

Increased density of low-K dielectric materials in semiconductor devices by applying a UV treatment

STRECK CHRISTOF

Increased stability of a complex material stack in a semiconductor device by providing fluorine enriched interfaces

RICHTER RALF

Non-insulating stressed material layers in a contact level of semiconductor devices