Inventor

LU DARSEN D

US36 patents

⚠️ This page may combine multiple inventors who share the name “LU DARSEN D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LU DARSEN D

IBM

Distributed decoupling capacitor

FinFET with reduced parasitic capacitance

Structure and method for advanced bulk fin isolation

Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices

Structure and method for advanced bulk fin isolation

FinFET with reduced parasitic capacitance

FinFET with reduced parasitic capacitance

Structure and method to make strained FinFET with improved junction capacitance and low leakage

Asymmetric finFET memory access transistor

Asymmetric finFET memory access transistor

Strain release in PFET regions

Radiation tolerant device structure

Semiconductor device including dielectrically isolated finFETs and buried stressor

Dielectric isolated fin with improved fin profile

Distributed decoupling capacitor

Dielectric isolated fin with improved fin profile

Semiconductor structures having increased channel strain using fin release in gate regions

Semiconductor structures having increased channel strain using fin release in gate regions

Semiconductor structures having increased channel strain using fin release in gate regions

Structure and method to make strained FinFET with improved junction capacitance and low leakage

FinFET with reduced parasitic capacitance

Distributed decoupling capacitor

Dielectric isolated fin with improved fin profile

Semiconductor structures having increased channel strain using fin release in gate regions

Distributed decoupling capacitor

Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices

Strain release in pFET regions

Dielectric isolated fin with improved fin profile

Strain release in PFET regions

Structure and method for advanced bulk fin isolation

Dielectric isolated fin with improved fin profile

Engineered substrate and device for co-integration of strained silicon and relaxed silicon

P-FET with graded silicon-germanium channel

GLOBALFOUNDRIES INC

Lateral bipolar junction transistor having graded SiGe base

FinFET PCM access transistor having gate-wrapped source and drain regions

FinFET PCM access transistor having gate-wrapped source and drain regions