Inventor
VERMA MANUJ
IN7 patents
Patents
7 patentsUS10031986B1Jul 24, 2018
System and method for creating a spice deck for path-based analysis of an electronic circuit design using a stage-based technique
CADENCE DESIGN SYSTEMS INC22 citations92
US7464349B1Dec 9, 2008
Method and system or generating a current source model of a gate
CADENCE DESIGN SYSTEMS INC9 citations83
US9589096B1Mar 7, 2017
Method and apparatus for integrating spice-based timing using sign-off path-based analysis
CADENCE DESIGN SYSTEMS INC12 citations82
US10289774B1May 14, 2019
Systems and methods for reuse of delay calculation in static timing analysis
CADENCE DESIGN SYSTEMS INC9 citations81
US9881123B1Jan 30, 2018
Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact
CADENCE DESIGN SYSTEMS INC12 citations81
US9529962B1Dec 27, 2016
System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design
CADENCE DESIGN SYSTEMS INC6 citations71
US11023636B1Jun 1, 2021
Methods, systems, and computer program product for characterizing an electronic design with a susceptibility window
CADENCE DESIGN SYSTEMS INC3 citations68