Inventor

ANDRY PAUL S

US110 patents

⚠️ This page may combine multiple inventors who share the name “ANDRY PAUL S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ANDRY PAUL S

IBM

Double-face heat removal of vertically integrated chip-stacks utilizing combined symmetric silicon carrier fluid cavity and micro-channel cold plate

Conductive through via process for electronic device carriers

Semiconductor integrated circuit chip packages having integrated microchannel cooling modules

High performance thin film transistor and active matrix process for flat panel displays

Method for fabricating self-aligned thin-film transistors to define a drain and source in a single photolithographic step

Advanced handler wafer bonding and debonding

Integrated circuit chip module with microchannel cooling device having specific fluid channel arrangement

Yield enchancement pixel structure for active matrix organic light-emitting diode displays

Optimal tungsten through wafer via and process of fabricating same

Double layer release temporary bond and debond processes and systems

Double layer release temporary bond and debond processes and systems

Flexible electronics for wearable healthcare sensors

Dies for RFID devices and sensor applications

Low temperature adhesive resins for wafer bonding

Composite wiring board with electrical through connections

Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers

Electronic module comprising memory and integrated circuit processor chips formed on a microchannel cooling device

Silicon-on-insulator structures for through via in silicon carriers

Tilted vertical alignment of liquid crystals employing inorganic thin film composition and ion beam treatment

Thin, flexible microsystem with integrated energy source

Reworkable electronic device assembly and method

Method and apparatus for filling vias

Liquid crystal display cell having liquid crystal molecules in vertical or substantially vertical alignment

Optimized annular copper TSV

Small area, robust silicon via structure and process

Metal induced self-aligned crystallization of Si layer for TFT

Modular, frequency-flexible, superconducting quantum processor architecture

Handler bonding and debonding for semiconductor dies

Handler bonding and debonding for semiconductor dies

Handler bonding and debonding for semiconductor dies

Handler bonding and debonding for semiconductor dies

Low temperature adhesive resins for wafer bonding

Microelectronic smart tags

Wafer level overmold for three dimensional surfaces

Dies for RFID devices and sensor applications

Method for forming patterns for semiconductor devices

Three-D power converter in three distinct strata

Assembly of a chip to a substrate

Integrated circuit assembly with cushion polymer layer

Low threshold voltage instability amorphous silicon field effect transistor structure and biasing for active matrix organic light-emitting diodes

ANDRY PAUL S

Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers

Silicon photonic chip optical coupling structures

Electronic module with carrier substrates, multiple integrated circuit (IC) chips and microchannel cooling device

Silicon carrier optoelectronic packaging

Optimized annular copper TSV

Process for wet singulation using a dicing singulation structure

High-yield method of exposing and contacting through-silicon vias

Silicon carrier optoelectronic packaging

Transferable probe tips

ANDERSON BRENT A

Silicon-on-insulator structures for through via in silicon carriers