Inventor

RANTA TERO TAPIO

US105 patents

⚠️ This page may combine multiple inventors who share the name “RANTA TERO TAPIO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RANTA TERO TAPIO

PSEMI CORP

AC coupling modules for bias ladders

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals

Cascode amplifier bias circuits

Constant Vds1 bias control for stacked transistor configuration

Gate drivers for stacked transistor amplifiers

Transient stabilized SOI FETs

Managed substrate effects for stabilized SOI FETs

Positive logic switch with selectable DC blocking circuit

Gate drivers for stacked transistor amplifiers

Power amplifier self-heating compensation circuit

Managed substrate effects for stabilized SOI FETs

Power amplifier self-heating compensation circuit

Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device

Body tie optimization for stacked transistor amplifier

Stacked FET switch bias ladders

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals

Methods and apparatuses for use in tuning reactance in a circuit device

RF switch with split tunable matching network

RF switch with split tunable matching network

Gate drivers for stacked transistor amplifiers

Gate drivers for stacked transistor amplifiers

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals

RF switch with split tunable matching network

Power amplifier self-heating compensation circuit

Power amplifier self-heating compensation circuit

Body tie optimization for stacked transistor amplifier

Controllable temperature coefficient bias circuit

Cascode amplifier bias circuits

Adaptive tuning networks with direct mapped multiple channel filter tuning

AC coupling modules for bias ladders

Multi-stage stacked power amplifier feedback circuit for improved performance

RF switch with split tunable matching network

Positive temperature coefficient bias compensation circuit

Integrated ultra-compact VSWR insensitive coupler

Transient stabilized cascode biasing

Current mirror bias compensation circuit

PEREGRINE SEMICONDUCTOR CORP

Positive logic digitally tunable capacitor

Body tie optimization for stacked transistor amplifier

Gate drivers for stacked transistor amplifiers

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals

Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device

Methods and apparatuses for use in tuning reactance in a circuit device

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals

RANTA TERO TAPIO

Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals

REEDY RONALD EUGENE

Methods and apparatuses for use in tuning reactance in a circuit device

BAWELL SHAWN

Digitally tuned capacitors with tapered and reconfigurable quality factors