Inventor

LEE HSIEN-HSIN SEAN

US37 patents

⚠️ This page may combine multiple inventors who share the name “LEE HSIEN-HSIN SEAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE HSIEN-HSIN SEAN

TAIWAN SEMICONDUCTOR MFG CO LTD

Memory circuit and cache circuit configuration

Memory circuit and cache circuit configuration

Standard cell and semiconductor device including anchor nodes and method of making

Standard cell and semiconductor device including anchor nodes

Integrated circuit and method for manufacturing the same

Method of designing a semiconductor device, system for implementing the method and standard cell

Method of generating modified layout for RC extraction

Method and apparatus for capacitance extraction

System and method for creating hybrid resistance and capacitance (RC) netlist using three-dimensional RC extraction and 2.5 dimensional RC extraction

Method of determining colorability of a semiconductor device and system for implementing the same

Multi-patterning graph reduction and checking flow method

Method of determining colorability of a semiconductor device and system for implementing the same

Method and system for verifying the design of an integrated circuit having multiple tiers

Method for layout generation with constrained hypergraph partitioning

Integrated circuit and method of manufacturing the same

Standard cell and semiconductor device including anchor nodes

Memory circuit and cache circuit configuration

Integrated circuit and method of manufacturing the same

Standard cell and semiconductor device including anchor nodes and method of making

Memory circuit and cache circuit configuration

Integrated circuit and system of manufacturing the same

Integrated circuit and method for manufacturing same

Mask shift resistance-inductance method for multiple patterning mask design and a method for performing the same

Multi-patterning mask decomposition method and system

Multi-patterning graph reduction and checking flow method

Multi-patterning graph reduction and checking flow method

Memory circuit and cache circuit configuration

Method of generating modified layout and system therefor

Mask design based on sensitivities to changes in pattern spacing

Method of determining colorability of a semiconductor device and system for implementing the same

Multi-layer semiconductor structures for fabricating inverter chains

Method, device and computer program product for integrated circuit layout generation

Systems and methods for tuning technology files

TAIWAN SEMICONDUCTOR MFG

Parasitic capacitance extraction for FinFETs

Multi-layer semiconductor structures for fabricating inverter chains

META PLATFORMS INC

Computer memory module processing device with cache storage

META PLATFORMS TECH LLC

Personalized online learning for artificial reality applications