Inventor
CHENG KENNETH CHUN KUEN
US42 patents
Patents
42 patentsUS11024577B1Jun 1, 2021
Embedded anti-fuses for small scale applications
IBM8 citations84
US11881431B2Jan 23, 2024
Anti-fuse with laterally extended liner
IBM3 citations75
US11848264B2Dec 19, 2023
Semiconductor structure with stacked vias having dome-shaped tips
IBM2 citations73
US11758819B2Sep 12, 2023
Magneto-resistive random access memory with laterally-recessed free layer
IBM2 citations73
US11315872B1Apr 26, 2022
Self-aligned top via
IBM2 citations73
US11244854B2Feb 8, 2022
Dual damascene fully aligned via in interconnects
IBM2 citations73
US11201056B2Dec 14, 2021
Pitch multiplication with high pattern fidelity
IBM2 citations73
US11183455B2Nov 23, 2021
Interconnects with enlarged contact area
IBM2 citations73
US10950493B1Mar 16, 2021
Interconnects having air gap spacers
IBM2 citations73
US12538714B2Jan 27, 2026
Magneto-resistive random access memory with laterally-recessed free layer
IBM0 citations62
US12406920B2Sep 2, 2025
Top via interconnect with airgap
IBM0 citations62
US12400912B2Aug 26, 2025
Dual-damascene fav interconnects with dielectric plug
IBM0 citations62
US12341100B2Jun 24, 2025
Copper interconnects with self-aligned hourglass-shaped metal cap
IBM0 citations62
US12315807B2May 27, 2025
Reducing copper line resistance
IBM0 citations62
US12266607B2Apr 1, 2025
Bottom barrier free interconnects without voids
IBM0 citations62
US12087624B2Sep 10, 2024
Beol tip-to-tip shorting and time dependent dielectric breakdown
IBM0 citations62
US12057395B2Aug 6, 2024
Top via interconnects without barrier metal between via and above line
IBM0 citations62
US12027416B2Jul 2, 2024
BEOL etch stop layer without capacitance penalty
IBM0 citations62
US11735475B2Aug 22, 2023
Removal of barrier and liner layers from a bottom of a via
IBM0 citations62
US11430690B2Aug 30, 2022
Interconnects having air gap spacers
IBM1 citations62
US11410879B2Aug 9, 2022
Subtractive back-end-of-line vias
IBM0 citations62
US11270913B2Mar 8, 2022
BEOL metallization formation
IBM0 citations62
US11205591B2Dec 21, 2021
Top via interconnect with self-aligned barrier layer
IBM1 citations62
US11201112B2Dec 14, 2021
Fully-aligned skip-vias
IBM1 citations62
US11177169B2Nov 16, 2021
Interconnects with gouged vias
IBM0 citations62
US11177170B2Nov 16, 2021
Removal of barrier and liner layers from a bottom of a via
IBM0 citations62
US11164815B2Nov 2, 2021
Bottom barrier free interconnects without voids
IBM0 citations62
US11127676B2Sep 21, 2021
Removal or reduction of chamfer for fully-aligned via
IBM1 citations62
US11094580B2Aug 17, 2021
Structure and method to fabricate fully aligned via with reduced contact resistance
IBM0 citations62
US12550708B2Feb 10, 2026
Top via interconnect with an embedded antifuse
IBM0 citations52
US12538785B2Jan 27, 2026
Fully-aligned and dielectric damage-less top via interconnect structure
IBM0 citations52
US12402329B2Aug 26, 2025
Top via containing random-access memory cross-bar array
IBM0 citations52
US12356638B2Jul 8, 2025
Metal-insulator-metal capacitor structure with enlarged capacitor area
IBM0 citations52
US11972977B2Apr 30, 2024
Fabrication of rigid close-pitch interconnects
IBM0 citations52
US11380641B2Jul 5, 2022
Pillar bump with noble metal seed layer for advanced heterogeneous integration
IBM0 citations52
US11289375B2Mar 29, 2022
Fully aligned interconnects with selective area deposition
IBM0 citations52
US11244853B2Feb 8, 2022
Fully aligned via interconnects with partially removed etch stop layer
IBM0 citations52
US11244897B2Feb 8, 2022
Back end of line metallization
IBM0 citations52
US11177163B2Nov 16, 2021
Top via structure with enlarged contact area with upper metallization level
IBM0 citations52
US11177214B2Nov 16, 2021
Interconnects with hybrid metal conductors
IBM0 citations52
US11164774B2Nov 2, 2021
Interconnects with spacer structure for forming air-gaps
IBM0 citations52
US12438047B2Oct 7, 2025
Double patterning with selectively deposited spacer
IBM0 citations50