Inventor

KOBURGER III CHARLES W

US143 patents

⚠️ This page may combine multiple inventors who share the name “KOBURGER III CHARLES W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KOBURGER III CHARLES W

IBM

Field effect transistor

Accessible chip stack and process of manufacturing thereof

Methods for forming uniform lithographic features

Forming capping layer over metal wire structure using selective atomic layer deposition

Method of forming a body contact using BOX modification

Plug strap process utilizing selective nitride and oxide etches

Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells

FinFETs and fin isolation structures

Borderless contact to diffusion with respect to gate conductor and methods for fabricating

Sub-lithographic semiconductor structures with non-constant pitch

FinFET with reduced capacitance

Single fin cut employing angled processing methods

Metal alloy cap integration

Sub-lithographic imaging techniques and processes

Silicon-on-insulator (SOI) read only memory (ROM) array and method of making a SOI ROM

Non-volatile switching and memory devices using vertical nanotubes

Sidewall image transfer (SIT) technologies

Low-k dielectric layer based upon carbon nanostructures

Borderless contact structures

Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions

Vertical carbon nanotube transistor integration

Self-aligned contact for closely spaced transistors

Forming wide dielectric-filled isolation trenches in semi-conductors

Method of self-aligning a trench isolation structure to an implanted well region

Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step

Method of forming borderless contacts

Borderless contact to diffusion with respect to gate conductor and methods for fabricating

Stress inducing contact metal in FinFET CMOS

Dual-metal self-aligned wires and vias

Hybrid copper interconnect structure and method of fabricating same

Sealed air gap for semiconductor chip

Dual mandrel sidewall image transfer processes

Air-dielectric for subtractive etch line and via metallization

FinFET devices

Shared gate for conventional planar device and horizontal CNT

Temporary etchable liner for forming air gap

Structure and method for improving storage latch susceptibility to single event upsets

Carbon nanotube conductor for trench capacitors

Microelectronic structure by selective deposition

Methods and structure for forming self-aligned borderless contacts for strain engineered logic devices

PONOTH SHOM

Borderless interconnect line structure self-aligned to upper and lower level contact vias

Borderless interconnect line structure self-aligned to upper and lower level contact vias

Structure for nano-scale metallization and method for fabricating same

YANG CHIH-CHAO

Hybrid copper interconnect structure and method of fabricating same

Method of fabricating a profile control in interconnect structures

DORIS BRUCE B

Parasitic capacitance reduction in MOSFET by airgap ild

HORAK DAVID V

Sealed air gap for semiconductor chip

BREYTA GREGORY

Semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device and a method of forming the semiconductor structure using a self-assembly approach

GLOBALFOUNDRIES INC

Sub-lithographic semiconductor structures with non-constant pitch

KOBURGER III CHARLES W

Mask free protection of work function material portions in wide replacement gate electrodes