Inventor

YANG CHIH-CHAO

US915 patents

⚠️ This page may combine multiple inventors who share the name “YANG CHIH-CHAO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YANG CHIH-CHAO

IBM

Method for wafer-wafer bonding

Nitride-enriched oxide-to-oxide 3D wafer bonding

Structures of and methods and tools for forming in-situ metallic/dielectric caps for interconnects

Reversible electric fuse and antifuse structures for semiconductor devices

Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same

Structure and method for monitoring stress-induced degradation of conductive interconnects

Structure and method for metal integration

Formation of embedded magnetic random-access memory devices

Void-free metallic interconnect structures with self-formed diffusion barrier layers

Copper interconnect with filled void

Skip via for metal interconnects

Formation of advanced interconnects

Self-aligned low resistance metallic interconnect structures

Contact having self-aligned air gap spacers

Treating copper interconnects

Advanced metal-to-metal direct bonding

FinFETs and fin isolation structures

Interconnect structure and method for forming the same

Micro-cavity MEMS device and method of fabricating same

Low-resistivity metallic interconnect structures with self-forming diffusion barrier layers

Surface nitridation in metal interconnects

Cobalt top layer advanced metallization for interconnects

Selective gate contact fill metallization

Semiconductor device with reduced via resistance

Integrated formation of Si and SiGe fins

Sub-lithographic semiconductor structures with non-constant pitch

Self-aligned vias formed using sacrificial metal caps

Single fin cut employing angled processing methods

Metal alloy cap integration

Nitrogen-containing metal cap for interconnect structures

High density planar magnetic domain wall memory apparatus

Hybrid interconnect structure for performance improvement and reliability enhancement

Large grain size conductive structure for narrow interconnect openings

Structure for interconnect structure containing various capping materials for electrical fuse and other related applications

Electrical fuse and method of making

Structure for stochastic integrated circuit personalization

Interconnect with recessed dielectric adjacent a noble metal cap

Interconnect structure with bi-layer metal cap

Simultaneous grain modulation for BEOL applications

Semiconductor structure for fuse and anti-fuse applications

YANG CHIH-CHAO

Pad bonding employing a self-aligned plated liner for adhesion enhancement

Interconnect structure containing non-damaged dielectric and a via gouging feature

Hybrid copper interconnect structure and method of fabricating same

3D via capacitor with a floating conductive plate for improved reliability

Redundant metal barrier structure for interconnect applications

Interconnect structure having a via with a via gouging feature and dielectric liner sidewalls for BEOL integration

Metal cap with ultra-low k dielectric material for circuit interconnect applications

CHENG KANGGUO

Replacement metal gate processing with reduced interlevel dielectric layer etch rate

FinFET fuse with enhanced current crowding

PONOTH SHOM

Borderless interconnect line structure self-aligned to upper and lower level contact vias