Inventor

HUANG TZE-CHIANG

US42 patents

⚠️ This page may combine multiple inventors who share the name “HUANG TZE-CHIANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUANG TZE-CHIANG

TAIWAN SEMICONDUCTOR MFG CO LTD

System on chip (SOC) current profile model for integrated voltage regulator (IVR) co-design

Power delivery for multi-chip-package using in-package voltage regulator

Memory macro including through-silicon via

Integrated circuit with radio frequency interconnect

Memory macro including through-silicon via

System and method for ESL modeling of machine learning

Integrated circuit with radio frequency interconnect

Transceiver group and associated router

Semiconductor device including a voltage regulator and an integrated circuit module

Integrated impedance measurement device and impedance measurement method thereof

Semiconductor device and method of manufacture

System on chip (SOC) current profile model for integrated voltage regulator (IVR) co-design

Metastable flip-flop based true random number generator (TRNG) structure and compiler for same

Integrated circuit die with memory macro including through-silicon via and method of forming the same

Integrated circuit with radio frequency interconnect

System and method for ESL modeling of machine learning

Semiconductor packages and methods of manufacturing thereof

Trim-based voltage regulator circuit and method

System and method for ESL modeling of machine learning

System on chip (SOC) current profile model for integrated voltage regulator (IVR) co-design

Semiconductor device and method of manufacture

Die to die interface circuit

Integrated impedance measurement device and impedance measurement method thereof

Die to die interface circuit

Power estimation

Power state-based voltage regulator circuit and method

Flip-flop based true random number generator (TRNG) structure and compiler for same

Power state coverage metric and method for estimating the same

Power estimation

Systems and methods for generating synthesizable netlists from register transfer level designs

System and method for estimating performance, power, area and cost (PPAC)

Processor power estimation

Electrical system level (ESL) battery discharge simulation

System and method for system-level parameter estimation

Power consumption estimation method for system on chip (SOC), system for implementing the method

Method and apparatus for speeding up gate-level simulation

GLOBAL UNICHIP CORP

Interface device and interface method for 3D semiconductor device

Semiconductor device in 3D stack with communication interface and managing method thereof

Interface for semiconductor device with symmetric bond pattern and method for arranging interface thereof

Interface for semiconductor device and interfacing method thereof

Data protection system and method thereof for 3D semiconductor device

GOEL SANDEEP KUMAR

DRAM repair architecture for wide I/O DRAM based 2.5D/3D system chips