Inventor

AMBATIPUDI SAI LALITH CHAITANYA

IN3 patents

Patents

3 patents

US8386828B1Feb 26, 2013

Circuit for estimating latency through a FIFO buffer

XILINX INC16 citations78

US11941248B2Mar 26, 2024

Compression of sparse tensors

XILINX INC0 citations51

US11842168B2Dec 12, 2023

Circuit architecture for determining threshold ranges and values of a dataset

XILINX INC0 citations38