Inventor

KAKAIYA UTKARSH Y

US54 patents

Patents

50 patents

US10228981B2Mar 12, 2019

High-performance input-output devices supporting scalable virtualization

INTEL CORP12 citations92

US11556436B2Jan 17, 2023

Memory enclaves using process address space identifiers in a scalable input/output (I/O) virtualization (S-IOV) architecture

INTEL CORP4 citations85

US11656916B2May 23, 2023

High-performance input-output devices supporting scalable virtualization

INTEL CORP2 citations73

US11474916B2Oct 18, 2022

Failover of virtual devices in a scalable input/output (I/O) virtualization (S-IOV) architecture

INTEL CORP2 citations72

US11513924B2Nov 29, 2022

Flexible memory mapped input/output (I/O) space definition for a virtual device in a scalable I/O virtualization (S-IOV) architecture

INTEL CORP2 citations71

US10762244B2Sep 1, 2020

Virtualization of process address space identifiers for scalable virtualization of input/output devices

INTEL CORP0 citations63

US11099880B2Aug 24, 2021

Virtualization of process address space identifiers for scalable virtualization of input/output devices

INTEL CORP1 citations63

US12591660B2Mar 31, 2026

Device security manager architecture for trusted execution environment input/output (TEE-IO) capable system-on-a-chip integrated devices

INTEL CORP0 citations62

US12556413B2Feb 17, 2026

Techniques to implement confidential computing with a remote device via use of trust domains

INTEL CORP0 citations62

US12386772B2Aug 12, 2025

Technologies for increasing link efficiency

INTEL CORP0 citations62

US12326818B2Jun 10, 2025

Unified address translation for virtualization of input/output devices

INTEL CORP0 citations62

US12271616B2Apr 8, 2025

Independently controlled DMA and CPU access to a shared memory region

INTEL CORP0 citations62

US12210660B2Jan 28, 2025

Cryptographic computing with legacy peripheral devices

INTEL CORP0 citations62

US12189542B2Jan 7, 2025

Technologies for secure device configuration and management

INTEL CORP0 citations62

US12164971B2Dec 10, 2024

High-performance input-output devices supporting scalable virtualization

INTEL CORP0 citations62

US12086082B2Sep 10, 2024

PASID based routing extension for scalable IOV systems

INTEL CORP0 citations62

US12013790B2Jun 18, 2024

Unified address translation for virtualization of input/output devices

INTEL CORP0 citations62

US11995462B2May 28, 2024

Techniques for virtual machine transfer and resource management

INTEL CORP0 citations62

US11740931B2Aug 29, 2023

Processing device, control unit, electronic device, method for the electronic device, and computer program for the electronic device

INTEL CORP0 citations62

US11734209B2Aug 22, 2023

Scalable interrupt virtualization for input/output devices

INTEL CORP0 citations62

US11698866B2Jul 11, 2023

Unified address translation for virtualization of input/output devices

INTEL CORP0 citations62

US11573870B2Feb 7, 2023

Zero copy host interface in a scalable input/output (I/O) virtualization (S-IOV) architecture

INTEL CORP0 citations62

US11556437B2Jan 17, 2023

Live migration of virtual devices in a scalable input/output (I/O) virtualization (S-IOV) architecture

INTEL CORP0 citations62

US11556363B2Jan 17, 2023

Techniques for virtual machine transfer and resource management

INTEL CORP0 citations62

US11461099B2Oct 4, 2022

System, apparatus and method for fine-grain address space selection in a processor

INTEL CORP0 citations62

US11416415B2Aug 16, 2022

Technologies for secure device configuration and management

INTEL CORP0 citations62

US11200183B2Dec 14, 2021

Scalable interrupt virtualization for input/output devices

INTEL CORP0 citations62

US11055147B2Jul 6, 2021

High-performance input-output devices supporting scalable virtualization

INTEL CORP0 citations62

US12117910B2Oct 15, 2024

Virtual device composition in a scalable input/output (I/O) virtualization (S-IOV) architecture

INTEL CORP0 citations61

US11550746B2Jan 10, 2023

Multi-uplink device enumeration and management

INTEL CORP0 citations61

US11526451B2Dec 13, 2022

Secure address translation services using bundle access control

INTEL CORP1 citations61

US12455701B2Oct 28, 2025

Scalable access control checking for cross-address-space data movement

INTEL CORP0 citations60

US12407764B2Sep 2, 2025

Securely exposing an accelerator to privileged system components

INTEL CORP0 citations60

US12443477B2Oct 14, 2025

Method and apparatus for high-performance page-fault handling for multi-tenant scalable accelerators

INTEL CORP0 citations59

US12292791B2May 6, 2025

Systems and methods for isolating an accelerated function unit and/or an accelerated function context

INTEL CORP0 citations59

US11966281B2Apr 23, 2024

Systems and methods for isolating an accelerated function unit and/or an accelerated function context

INTEL CORP0 citations59

US11307925B2Apr 19, 2022

Systems and methods for isolating an accelerated function unit and/or an accelerated function context

INTEL CORP0 citations59

US12112204B2Oct 8, 2024

Modular accelerator function unit (AFU) design, discovery, and reuse

INTEL CORP0 citations58

US11416300B2Aug 16, 2022

Modular accelerator function unit (AFU) design, discovery, and reuse

INTEL CORP1 citations58

US11816040B2Nov 14, 2023

Device memory protection for supporting trust domains

INTEL CORP0 citations52

US11360925B2Jun 14, 2022

Method and apparatus for host adaptation to a change of persona of a configurable integrated circuit die

INTEL CORP0 citations52

US12292840B2May 6, 2025

Secure direct peer-to-peer memory access requests between devices

INTEL CORP0 citations51

US12164444B2Dec 10, 2024

Device, method, and system to identify a page request to be processed after a reset event

INTEL CORP0 citations51

US12045640B2Jul 23, 2024

System, apparatus and method for accessing multiple address spaces via a data mover

INTEL CORP0 citations51

US11907744B2Feb 20, 2024

System, apparatus and method for enabling fine-grain quality of service or rate control for work submissions

INTEL CORP0 citations51

US11599621B2Mar 7, 2023

Apparatuses, methods, and systems for verification of input-output memory management unit to device attachment

INTEL CORP0 citations51

Showing the top 50 of 54 patents by PatentIndex Score.

KAKAIYA UTKARSH Y

Patents

High-performance input-output devices supporting scalable virtualization

Memory enclaves using process address space identifiers in a scalable input/output (I/O) virtualization (S-IOV) architecture

High-performance input-output devices supporting scalable virtualization

Failover of virtual devices in a scalable input/output (I/O) virtualization (S-IOV) architecture

Flexible memory mapped input/output (I/O) space definition for a virtual device in a scalable I/O virtualization (S-IOV) architecture

Securely exposing an accelerator to privileged system components

Extending a root complex to encompass an external component

Validating an image for a reconfigurable device

Infrastructure processing unit

Virtualization of process address space identifiers for scalable virtualization of input/output devices

Virtualization of process address space identifiers for scalable virtualization of input/output devices

Device security manager architecture for trusted execution environment input/output (TEE-IO) capable system-on-a-chip integrated devices

Techniques to implement confidential computing with a remote device via use of trust domains

Technologies for increasing link efficiency

Unified address translation for virtualization of input/output devices

Independently controlled DMA and CPU access to a shared memory region

Cryptographic computing with legacy peripheral devices

Technologies for secure device configuration and management

High-performance input-output devices supporting scalable virtualization

PASID based routing extension for scalable IOV systems

Unified address translation for virtualization of input/output devices

Techniques for virtual machine transfer and resource management

Processing device, control unit, electronic device, method for the electronic device, and computer program for the electronic device

Scalable interrupt virtualization for input/output devices

Unified address translation for virtualization of input/output devices

Zero copy host interface in a scalable input/output (I/O) virtualization (S-IOV) architecture

Live migration of virtual devices in a scalable input/output (I/O) virtualization (S-IOV) architecture

Techniques for virtual machine transfer and resource management

System, apparatus and method for fine-grain address space selection in a processor

Technologies for secure device configuration and management

Scalable interrupt virtualization for input/output devices

High-performance input-output devices supporting scalable virtualization

Virtual device composition in a scalable input/output (I/O) virtualization (S-IOV) architecture

Multi-uplink device enumeration and management

Secure address translation services using bundle access control

Scalable access control checking for cross-address-space data movement

Securely exposing an accelerator to privileged system components

Method and apparatus for high-performance page-fault handling for multi-tenant scalable accelerators

Systems and methods for isolating an accelerated function unit and/or an accelerated function context

Systems and methods for isolating an accelerated function unit and/or an accelerated function context

Systems and methods for isolating an accelerated function unit and/or an accelerated function context

Modular accelerator function unit (AFU) design, discovery, and reuse

Modular accelerator function unit (AFU) design, discovery, and reuse

Device memory protection for supporting trust domains

Method and apparatus for host adaptation to a change of persona of a configurable integrated circuit die

Secure direct peer-to-peer memory access requests between devices

Device, method, and system to identify a page request to be processed after a reset event

System, apparatus and method for accessing multiple address spaces via a data mover

System, apparatus and method for enabling fine-grain quality of service or rate control for work submissions

Apparatuses, methods, and systems for verification of input-output memory management unit to device attachment