Inventor
CADOURI EITAN
US16 patents
⚠️ This page may combine multiple inventors who share the name “CADOURI EITAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
PDF SOLUTIONS INC
8 patentsUS6826738B2Nov 30, 2004
Optimization of die placement on wafers
PDF SOLUTIONS INC213 citations98
US7220605B1May 22, 2007
Selecting dice to test using a yield map
PDF SOLUTIONS INC7 citations73
US7039543B1May 2, 2006
Transforming yield information of a semiconductor fabrication process
PDF SOLUTIONS INC6 citations62
US7508071B2Mar 24, 2009
Adjusting die placement on a semiconductor wafer to increase yield
PDF SOLUTIONS INC1 citations51
US7440869B1Oct 21, 2008
Mapping yield information of semiconductor dice
PDF SOLUTIONS INC1 citations51
US7334205B1Feb 19, 2008
Optimization of die placement on wafers
PDF SOLUTIONS INC0 citations51
US7190183B1Mar 13, 2007
Selecting die placement on a semiconductor wafer to reduce test time
PDF SOLUTIONS INC0 citations51
US7169638B1Jan 30, 2007
Adjusting die placement on a semiconductor wafer to increase yield
PDF SOLUTIONS INC1 citations51
CADENCE DESIGN SYSTEMS INC
6 patentsUS7904852B1Mar 8, 2011
Method and system for implementing parallel processing of electronic design automation tools
CADENCE DESIGN SYSTEMS INC20 citations86
US7913206B1Mar 22, 2011
Method and mechanism for performing partitioning of DRC operations
CADENCE DESIGN SYSTEMS INC17 citations83
US7555736B2Jun 30, 2009
Method and system for using pattern matching to process an integrated circuit design
CADENCE DESIGN SYSTEMS INC12 citations83
US7657856B1Feb 2, 2010
Method and system for parallel processing of IC design layouts
CADENCE DESIGN SYSTEMS INC15 citations82
US7617465B1Nov 10, 2009
Method and mechanism for performing latch-up check on an IC design
CADENCE DESIGN SYSTEMS INC2 citations62
US7908579B2Mar 15, 2011
Method and mechanism for extraction and recognition of polygons in an IC design
CADENCE DESIGN SYSTEMS INC5 citations54