Inventor
YEUNG GUS WAI-YAN
US16 patents
Patents
16 patentsUS6134164AOct 17, 2000
Sensing circuit for a memory cell array
IBM412 citations99
US6243776B1Jun 5, 2001
Selectable differential or single-ended mode bus
IBM112 citations97
US6157216ADec 5, 2000
Circuit driver on SOI for merged logic and memory circuits
IBM140 citations97
US5831896ANov 3, 1998
Memory cell
IBM56 citations96
US6915385B1Jul 5, 2005
Apparatus for unaligned cache reads and methods therefor
IBM34 citations92
US6338128B1Jan 8, 2002
System and method for invalidating an entry in a translation unit
IBM24 citations92
US6195280B1Feb 27, 2001
Memory system having a unidirectional bus and method for communicating therewith
IBM17 citations92
US5953745ASep 14, 1999
Redundant memory array
IBM32 citations92
US6108255AAug 22, 2000
Conditional restore for RAM based on feedback from a RAM cell to precharge circuitry
IBM10 citations74
US6064616AMay 16, 2000
Conditional restore for SRAM
IBM6 citations74
US6081458AJun 27, 2000
Memory system having a unidirectional bus and method for communicating therewith
IBM11 citations73
US5706237AJan 6, 1998
Self-restore circuit with soft error protection for dynamic logic circuits
IBM13 citations73
US6191620B1Feb 20, 2001
Sense amplifier/comparator circuit and data comparison method
IBM11 citations70
US6025741AFeb 15, 2000
Conditional restore for execution unit
IBM4 citations63
US6737888B1May 18, 2004
Method for skipping a latch in timing-sensitive dynamic circuits of a multi-clocked system with unspecific underlap requirement
IBM5 citations62
US5784330AJul 21, 1998
Evenly distributed RC delay word line decoding and mapping
IBM5 citations61