P

Inventor

CHAO HUNG-HSIANG JONATHAN

US35 patents
⚠️ This page may combine multiple inventors who share the name “CHAO HUNG-HSIANG JONATHAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

UNIV POLYTECHNIC

15 patents
US6667984B1Dec 23, 2003

Methods and apparatus for arbitrating output port contention in a switch having virtual output queuing

UNIV POLYTECHNIC124 citations98
US6487213B1Nov 26, 2002

Methods and apparatus for fairly arbitrating contention for an output port

UNIV POLYTECHNIC93 citations98
US6081507AJun 27, 2000

Methods and apparatus for handling time stamp aging

UNIV POLYTECHNIC136 citations97
US7046661B2May 16, 2006

Scheduling the dispatch of cells in non-empty virtual output queues of multistage switches using a pipelined hierarchical arbitration scheme

UNIV POLYTECHNIC46 citations96
US6389031B1May 14, 2002

Methods and apparatus for fairly scheduling queued packets using a ram-based search engine

UNIV POLYTECHNIC181 citations96
US6449283B1Sep 10, 2002

Methods and apparatus for providing a fast ring reservation arbitration

UNIV POLYTECHNIC133 citations93
US7894343B2Feb 22, 2011

Packet sequence maintenance with load balancing, and head-of-line blocking avoidance in a switch

UNIV POLYTECHNIC28 citations92
US6940851B2Sep 6, 2005

Scheduling the dispatch of cells in non-empty virtual output queues of multistage switches using a pipelined arbitration scheme

UNIV POLYTECHNIC39 citations92
US6370144B1Apr 9, 2002

Methods and apparatus for shaping queued packets using a two-dimensional RAM-based search engine

UNIV POLYTECHNIC42 citations90
US7852829B2Dec 14, 2010

Packet reassembly and deadlock avoidance for use in a packet switch

UNIV POLYTECHNIC11 citations84
US7792118B2Sep 7, 2010

Switch module memory structure and per-destination queue flow control for use in a switch

UNIV POLYTECHNIC14 citations84
US7103056B2Sep 5, 2006

Scheduling the dispatch of cells in multistage switches using a hierarchical arbitration scheme for matching non-empty virtual output queues of a module with outgoing links of the module

UNIV POLYTECHNIC15 citations84
US7203202B2Apr 10, 2007

Arbitration using dual round robin matching with exhaustive service of winning virtual output queue

UNIV POLYTECHNIC15 citations82
US7986691B2Jul 26, 2011

Maintaining packet sequence using cell flow control

UNIV POLYTECHNIC4 citations63
USRE42600EAug 9, 2011

Scheduling the dispatch of cells in non-empty virtual output queues of multistage switches using a pipelined arbitration scheme

UNIV POLYTECHNIC0 citations41

BANDO MASANORI

4 patents

CHAO HUNG-HSIANG JONATHAN

3 patents

(unassigned)

2 patents

POLYTECHNIC INST OF NEW YORK U

2 patents

POLITECHNIC INST UNIV NEW YORK

2 patents

FUTUREWEI TECHNOLOGIES INC

2 patents

OKI EIJI

2 patents

ALCATEL LUCENT USA INC

1 patent

PARK JINSOO

1 patent

AT & T IP I LP

1 patent