Inventor

YAARI YAAKOV

IL42 patents

⚠️ This page may combine multiple inventors who share the name “YAARI YAAKOV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YAARI YAAKOV

INTEL CORP

Processor executing unpack instruction to interleave data elements from two packed data

Method for unpacking a plurality of packed data into a result packed data

Microprocessor capable of unpacking packed data

Method for packing a plurality of packed data elements in response to a pack instruction

Processor performing packed data multiplication

Method for performing shift operations on packed data

Microprocessor capable of unpacking packed data in response to a unpack instruction

Apparatus for performing packed shift operations

Apparatus for performing packed shift operations

Processor for performing shift operations on packed data

Method for multiplying packed data

Pipeline system for executing predicted branch target instruction in a cycle concurrently with the execution of branch instruction

Method for performing population counts on packed data types

Method and apparatus for performing packed shift operations

Method and apparatus for providing packed shift operations in a processor

Method and apparatus for providing packed shift operations in a processor

Method and apparatus for providing packed shift operations in a processor

Processor capable of executing packed shift operations

Orderly storing of corresponding packed bytes from first and second source registers in result register

Packing saturated lower 8-bit elements from two source registers of packed 16-bit elements

Interleaving half of packed data elements of size specified in instruction and stored in two source registers

Executing unpack instruction and pack instruction with saturation on packed data elements from two source operand registers

Processor executing unpack and pack instructions specifying two source packed data operands and saturation

Packing in destination register half of each element with saturation from two source packed data registers

Packing odd bytes from two source registers of packed data

Packing lower half bits of signed data elements in two source registers in a destination register with saturation

Method and apparatus for unpacking and moving packed data

Interleaving saturated lower half of data elements from two source registers of packed data

Method and apparatus for executing packed shift operations

PELEG ALEXANDER

Execution of instruction with element size control bit to interleavingly store half packed data elements of source registers in same size destination register

Packing two packed signed data in registers with saturation

Packing signed word elements from two source registers to saturated signed byte elements in destination register

Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation

Processor executing pack and unpack instructions

IBM

Method and system for detecting runtime defects in a program by comparing correct and incorrect runs

Method for validation of binary code transformations

Predicting outcome based on input

Hardware-based edge profiling

HEIPER ANDRE

Test selection

TZOREF RACHEL

Performance optimization based on data accesses during critical sections

CITRON DANIEL

Detecting and optimizing false sharing

YAARI YAAKOV

Data object profiling during program execution