Inventor
ROTH CHARLES P
US37 patents
⚠️ This page may combine multiple inventors who share the name “ROTH CHARLES P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ANALOG DEVICES INC
18 patentsUS7028165B2Apr 11, 2006
Processor stalling
ANALOG DEVICES INC66 citations98
US6948056B1Sep 20, 2005
Maintaining even and odd array pointers to extreme values by searching and comparing multiple elements concurrently where a pointer is adjusted after processing to account for a number of pipeline stages
ANALOG DEVICES INC422 citations98
US6986026B2Jan 10, 2006
Single-step processing and selecting debugging modes
ANALOG DEVICES INC31 citations88
US7155570B1Dec 26, 2006
FIFO write/LIFO read trace buffer with software and hardware loop compression
ANALOG DEVICES INC13 citations84
US6898693B1May 24, 2005
Hardware loops
ANALOG DEVICES INC15 citations84
US7168032B2Jan 23, 2007
Data synchronization for a test access port
ANALOG DEVICES INC10 citations83
US7272705B2Sep 18, 2007
Early exception detection
ANALOG DEVICES INC6 citations74
US6976151B1Dec 13, 2005
Decoding an instruction portion and forwarding part of the portion to a first destination, re-encoding a different part of the portion and forwarding to a second destination
ANALOG DEVICES INC8 citations74
US6920515B2Jul 19, 2005
Early exception detection
ANALOG DEVICES INC6 citations74
US7069420B1Jun 27, 2006
Decode and dispatch of multi-issue and multiple width instructions
ANALOG DEVICES INC4 citations63
US7065636B2Jun 20, 2006
Hardware loops and pipeline system using advanced generation of loop parameters
ANALOG DEVICES INC4 citations63
US7043582B2May 9, 2006
Self-nesting interrupts
ANALOG DEVICES INC2 citations62
US7366876B1Apr 29, 2008
Efficient emulation instruction dispatch based on instruction width
ANALOG DEVICES INC3 citations61
US7082516B1Jul 25, 2006
Aligning instructions using a variable width alignment engine having an intelligent buffer refill mechanism
ANALOG DEVICES INC4 citations60
US7472259B2Dec 30, 2008
Multi-cycle instructions
ANALOG DEVICES INC1 citations52
US6920547B2Jul 19, 2005
Register adjustment based on adjustment values determined at multiple stages within a pipeline of a processor
ANALOG DEVICES INC1 citations52
US7036000B2Apr 25, 2006
Valid bit generation and tracking in a pipelined processor
ANALOG DEVICES INC0 citations51
US7360059B2Apr 15, 2008
Variable width alignment engine for aligning instructions based on transition between buffers
ANALOG DEVICES INC1 citations50
INTEL CORP
13 patentsUS6823448B2Nov 23, 2004
Exception handling using an exception pipeline in a pipelined processor
INTEL CORP69 citations96
US6754808B1Jun 22, 2004
Valid bit generation and tracking in a pipelined processor
INTEL CORP51 citations95
US6748523B1Jun 8, 2004
Hardware loops
INTEL CORP19 citations92
US6665795B1Dec 16, 2003
Resetting a programmable processor
INTEL CORP18 citations92
US7100033B2Aug 29, 2006
Controlling the timing of test modes in a multiple processor system
INTEL CORP18 citations80
US6842812B1Jan 11, 2005
Event handling
INTEL CORP9 citations74
US6766444B1Jul 20, 2004
Hardware loops
INTEL CORP11 citations74
US6829701B2Dec 7, 2004
Watchpoint engine for a pipelined processor
INTEL CORP4 citations63
US6789184B1Sep 7, 2004
Instruction address generation and tracking in a pipelined processor
INTEL CORP5 citations63
US6728870B1Apr 27, 2004
Register move operations
INTEL CORP4 citations63
US6760800B1Jul 6, 2004
Event vector table override
INTEL CORP2 citations62
US6789187B2Sep 7, 2004
Processor reset and instruction fetches
INTEL CORP0 citations52
US6763453B2Jul 13, 2004
Security on hardware loops
INTEL CORP0 citations52