Inventor
CHIN BRYAN W
US12 patents
⚠️ This page may combine multiple inventors who share the name “CHIN BRYAN W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CAVIUM INC
10 patentsUS9208103B2Dec 8, 2015
Translation bypass in multi-stage address translation
CAVIUM INC22 citations92
US9639476B2May 2, 2017
Merged TLB structure for multiple sequential address translations
CAVIUM INC15 citations84
US9268694B2Feb 23, 2016
Maintenance of cache and tags in a translation lookaside buffer
CAVIUM INC14 citations84
US9645941B2May 9, 2017
Collapsed address translation with multiple page sizes
CAVIUM INC10 citations82
US9372800B2Jun 21, 2016
Inter-chip interconnect protocol for a multi-chip system
CAVIUM INC5 citations72
US9703669B2Jul 11, 2017
Apparatus and method for distributed instruction trace in a processor system
CAVIUM INC2 citations71
US9404970B2Aug 2, 2016
Debug interface for multiple CPU cores
CAVIUM INC3 citations67
US9928193B2Mar 27, 2018
Distributed timer subsystem
CAVIUM INC0 citations51
US9568944B2Feb 14, 2017
Distributed timer subsystem across multiple devices
CAVIUM INC1 citations51
US10042778B2Aug 7, 2018
Collapsed address translation with multiple page sizes
CAVIUM INC0 citations50