Inventor

FLEISCHER BRUCE M

US55 patents

⚠️ This page may combine multiple inventors who share the name “FLEISCHER BRUCE M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FLEISCHER BRUCE M

IBM

Soft error detection for latches

Aligning precision converted vector data using mask indicating offset relative to element boundary corresponding to precision type

Local bypass in memory computing

Low latency data exchange

Address generation in an active memory device

System and method for a floating point unit with feedback prior to normalization and rounding

Processor design for extended-precision arithmetic

Fast comparator circuit

Bicmos driver circuits with improved low output level

Active memory device gather, scatter, and filter

On-chip traffic prioritization in memory

Power management for in-memory computer systems

Self-resetting CMOS parallel adder with a bubble pipelined architecture, tri-rail merging logic, and enhanced testability

On-chip traffic prioritization in memory

Margin improvement for configurable local clock buffer

Systems, methods and computer program products for providing a combined moduli-9 and 3 residue generator

System and method for performing decimal to binary conversion

Scheme to optimize scan chain ordering in designs

Executing a composite scalar-vector VLIW instruction having a repeat field

Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution

High bandwidth low latency data exchange between processing elements

High bandwidth low latency data exchange between processing elements

On-chip traffic prioritization in memory

Test structure to measure delay variability mismatch of digital logic paths

Chaining between exposed vector pipelines

Local bypass for in memory computing

Power management for a computer system

Low latency data exchange

Chaining between exposed vector pipelines

Power management for a computer system

Main processor support of tasks performed in memory

Main processor support of tasks performed in memory

Exposed-pipeline processing element with rollback

Exposed-pipeline processing element with rollback

FLEISCHER BRUCE M

Soft error detection for latches

Predication in a vector processor

Predication in a vector processor

Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry

Automated critical area allocation in a physical synthesized hierarchical design

Vector register file

Vector register file

Method and system for a wiring-efficient permute unit

Gather/scatter of multiple data elements with packed loading/storing into /from a register file entry

Vector processing in an active memory device

Vector processing in an active memory device

Register file soft error recovery

EICHENBERGER ALEXANDRE E

All-to-all permutation of vector elements based on a permutation pattern encoded in mantissa and exponent bits in a floating-point SIMD architecture

SIMD compare instruction using permute logic for distributed register files

ASAAD SAMEH

Multi-petascale highly efficient parallel supercomputer

GLOBALFOUNDRIES INC

Multi-petascale highly efficient parallel supercomputer