P

Inventor

SHARMA SAURABH

US45 patents
⚠️ This page may combine multiple inventors who share the name “SHARMA SAURABH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

29 patents
US10861126B1Dec 8, 2020

Asynchronous execution mechanism

INTEL CORP5 citations84
US10424107B2Sep 24, 2019

Hierarchical depth buffer back annotaton

INTEL CORP5 citations81
US12293462B2May 6, 2025

Tile sequencing mechanism

INTEL CORP1 citations72
US10146691B2Dec 4, 2018

System and method for performing partial cache line writes without fill-reads or byte enables

INTEL CORP3 citations72
US10102609B1Oct 16, 2018

Low granularity coarse depth test efficiency enhancement

INTEL CORP4 citations72
US9824412B2Nov 21, 2017

Position-only shading pipeline

INTEL CORP5 citations70
US11494867B2Nov 8, 2022

Asynchronous execution mechanism

INTEL CORP0 citations62
US11263720B2Mar 1, 2022

Frequent data value compression for graphics processing units

INTEL CORP0 citations62
US11250539B2Feb 15, 2022

Low granularity coarse depth test efficiency enhancement

INTEL CORP0 citations62
US11710269B2Jul 25, 2023

Position-based rendering apparatus and method for multi-die/GPU graphics processing

INTEL CORP0 citations61
US11403805B2Aug 2, 2022

Position-based rendering apparatus and method for multi-die/GPU graphics processing

INTEL CORP0 citations61
US11204801B2Dec 21, 2021

Method and apparatus for scheduling thread order to improve cache efficiency

INTEL CORP0 citations61
US10997771B2May 4, 2021

Position-based rendering apparatus and method for multi-die/GPU graphics processing

INTEL CORP0 citations61
US11900539B2Feb 13, 2024

Tile sequencing mechanism

INTEL CORP0 citations60
US11250627B2Feb 15, 2022

Tile sequencing mechanism

INTEL CORP0 citations60
US11640693B2May 2, 2023

Dynamically enabling tiling in 3D workloads

INTEL CORP0 citations59
US11615584B2Mar 28, 2023

Hierarchical depth buffer back annotation

INTEL CORP0 citations59
US11176736B2Nov 16, 2021

Dynamically enabling tiling in 3D workloads

INTEL CORP0 citations59
US11080925B2Aug 3, 2021

Hierarchical depth buffer back annotation

INTEL CORP0 citations59
US10916052B2Feb 9, 2021

Dynamically enabling tiling in 3D workloads

INTEL CORP0 citations59
US10769751B2Sep 8, 2020

Single input multiple data processing mechanism

INTEL CORP0 citations51
US10748238B2Aug 18, 2020

Frequent data value compression for graphics processing units

INTEL CORP0 citations51
US10748242B2Aug 18, 2020

Low granularity coarse depth test efficiency enhancement

INTEL CORP0 citations51
US10546362B2Jan 28, 2020

Method and apparatus for adaptive pixel hashing for graphics processors

INTEL CORP0 citations51
US10417730B2Sep 17, 2019

Single input multiple data processing mechanism

INTEL CORP0 citations51
US10262388B2Apr 16, 2019

Frequent data value compression for graphics processing units

INTEL CORP0 citations51
US9836809B2Dec 5, 2017

Method and apparatus for adaptive pixel hashing for graphics processors

INTEL CORP0 citations51
US9846962B2Dec 19, 2017

Optimizing clipping operations in position only shading tile deferred renderers

INTEL CORP0 citations50
US10140678B2Nov 27, 2018

Specialized code paths in GPU processing

INTEL CORP0 citations48

ADVANCED MICRO DEVICES INC

8 patents

GOOGLE INC

1 patent

MANDO CORP

1 patent

WEI LIANG

1 patent

KLA TENCOR CORP

1 patent

SHARMA SAURABH

1 patent

DRAVID VINAYAK P

1 patent

SAMSUNG ELECTRONICS CO LTD

1 patent

ADOBE INC

1 patent