Inventor
HEDDES MATTHEUS CORNELIS ANTONIUS ADRIANUS
US15 patents
Patents
15 patentsUS10176096B2Jan 8, 2019
Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches
QUALCOMM INC2 citations73
US9740621B2Aug 22, 2017
Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods
QUALCOMM INC3 citations73
US10936943B2Mar 2, 2021
Providing flexible matrix processors for performing neural network convolution in matrix-processor-based devices
QUALCOMM INC3 citations71
US10747501B2Aug 18, 2020
Providing efficient floating-point operations using matrix processors in processor-based systems
QUALCOMM INC4 citations71
US10725740B2Jul 28, 2020
Providing efficient multiplication of sparse matrices in matrix-processor-based devices
QUALCOMM INC5 citations71
US10236917B2Mar 19, 2019
Providing memory bandwidth compression in chipkill-correct memory architectures
QUALCOMM INC4 citations69
US10838862B2Nov 17, 2020
Memory controllers employing memory capacity compression, and related processor-based systems and methods
QUALCOMM INC1 citations62
US10191850B2Jan 29, 2019
Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system
QUALCOMM INC1 citations62
US10176090B2Jan 8, 2019
Providing memory bandwidth compression using adaptive compression in central processing unit (CPU)-based systems
QUALCOMM INC1 citations62
US10503661B2Dec 10, 2019
Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based system
QUALCOMM INC0 citations52
US10152261B2Dec 11, 2018
Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system
QUALCOMM INC0 citations52
US10146693B2Dec 4, 2018
Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system
QUALCOMM INC1 citations52
US10067706B2Sep 4, 2018
Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system
QUALCOMM INC0 citations52
US10467092B2Nov 5, 2019
Providing space-efficient storage for dynamic random access memory (DRAM) cache tags
QUALCOMM INC0 citations41
US10055158B2Aug 21, 2018
Providing flexible management of heterogeneous memory systems using spatial quality of service (QoS) tagging in processor-based systems
QUALCOMM INC0 citations40