Inventor

DJURDJEVIC IVANA

US20 patents

⚠️ This page may combine multiple inventors who share the name “DJURDJEVIC IVANA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DJURDJEVIC IVANA

SEAGATE TECHNOLOGY LLC

Mitigation of error correction failure due to trapping sets

Mitigation of write errors in multi-level cell flash memory through adaptive error correction code decoding

Communication channel with Reed-Solomon encoding and single parity check

Mitigation of error correction failure due to trapping sets

Low density parity check (LDPC) decoder with pre-saturation compensation

Method and apparatus for LDPC decoding using indexed messages

Read policy for system data of solid state drives

LSI CORP

Methods and systems for reducing decoder error floor for an electronic non-volatile computer storage apparatus

Generating partially sparse generator matrix for a quasi-cyclic low-density parity-check encoder

Systems and methods for data dependent inter-track interference cancellation

Noise predictive filter adaptation for inter-track interference cancellation

HITACHI GLOBAL STORAGE TECH NL

Techniques for generating bit reliability information in a post-processor using an error correction constraint

Techniques for generating bit reliability information in the post processor

WESTERN DIGITAL TECH INC

Minimizing redundancy for stuck bit coding

Stuck bits encoding and decoding on a storage device

WILSON BRUCE A

Error control in a flash memory device

LI ZONGWANG

Techniques for correcting errors using iterative decoding

TONG PO

Symmetric diagonal interleaving and encoding/decoding circuit and method

GALBRAITH RICHARD LEO

Systems using low density parity check codes for correcting errors

ZELDER OSKAR

Method for the production of glutaconate