Inventor

SANKARANARAYANAN SUNDARARAJAN

US52 patents

⚠️ This page may combine multiple inventors who share the name “SANKARANARAYANAN SUNDARARAJAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SANKARANARAYANAN SUNDARARAJAN

SEAGATE TECHNOLOGY LLC

Read retry operations where likelihood value assignments change sign at different read voltages for each read retry

Read retry operations with read reference voltages ranked for different page populations of a memory

Adaptive read threshold voltage tracking with charge leakage mitigation using threshold voltage offsets

Mitigation of error correction failure due to trapping sets

Read disturb detection based on dynamic bit error rate estimation

Read retry operations with estimation of written data based on syndrome weights

Read retry for non-volatile memories

Zone based timing recovery for bit patterned media

Adaptive read threshold voltage tracking with bit error rate estimation based on non-linear syndrome weight mapping

Independent read threshold voltage tracking for multiple dependent read threshold voltages using syndrome weights

Establishing parameters of subsequent read retry operations based on syndrome weights of prior failed decodings

Framework for balancing robustness and latency during collection of statistics from soft reads

Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory

Estimating read reference voltage based on disparity and derivative metrics

Adjusting log likelihood ratio values to compensate misplacement of read voltages

Multiple retry reads in a read channel of a memory

Read threshold voltage adaptation using bit error rates based on decoded data

Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory

Mitigation of error correction failure due to trapping sets

Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory

Adaptive read threshold voltage tracking with separate characterization on each side of voltage distribution about distribution mean

Low density parity check (LDPC) decoder with pre-saturation compensation

Framework for balancing robustness and latency during collection of statistics from soft reads

Read retry for non-volatile memories

Reordered data deduplication in storage devices

Reordered local data deduplication in storage devices

Detecting track information from overlapping signals read from a data storage medium

Systems and methods for directed soft data perturbation in layered decoding

Adaptive read threshold voltage tracking with gap estimation between default read threshold voltages

Mitigating data errors in a storage device

Mitigating data errors in a storage device

Data compression with redundancy removal across boundaries of compression search engines

Adaptive read threshold voltage tracking with charge leakage mitigation using charge leakage settling time

Adaptive read threshold voltage tracking with gap estimation between adjacent read threshold voltages

Multiple retry reads in a read channel of a memory

Refresh, run, aggregate decoder recovery

Refresh, run, aggregate decoder recovery

Time-multiplexed single input single output (SISO) data recovery channel

MICRON TECHNOLOGY INC

Read-time overhead and power optimizations with command queues in memory device

Using duplicate data for improving error correction capability

Concurrent page cache resource access in a multi-plane memory device

Using duplicate data for improving error correction capability

Controlling variation of valid data counts in garbage collection source blocks

Controlling variation of valid data counts in garbage collection source blocks

Memory device status push within memory sub-system

Read-time overhead and power optimizations with command queues in memory device

Second read initialization on latch-limited memory device

Storing sequential and random data in different layouts

Accessing memory devices via switchable channels

LSI CORP

Flash memory reference voltage detection with tracking of cross-points of cell voltage distributions using histograms