Inventor

BRUCK JEHOSHUA

US50 patents

⚠️ This page may combine multiple inventors who share the name “BRUCK JEHOSHUA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BRUCK JEHOSHUA

IBM

Method and means for encoding and rebuilding the data contents of up to two unavailable DASDS in a DASD array using simple non-recursive diagonal and row parity

Method and system for performing partial-sum queries on a data cube

Autonomous system for recognition of patterns formed by stored data during computer memory scrubbing

Method of simultaneously attempting parallel path connections in a multi-stage interconnection network

Flash-flooding multi-stage interconnection network with parallel path seeking switching elements

Variable cyclic redundancy coding method and apparatus for use in a multistage network

Method and apparatus for tolerating faults in mesh architectures

Multi-stage interconnection network with selectable function switching apparatus

Method for generating hierarchical fault-tolerant mesh architectures

Method and apparatus for a fault-tolerant mesh with spare nodes

Adaptive switching apparatus for multi-stage networks

System for selectively packing together datablocks and efficiently routing independent of network topology in a parallel computer system in accordance with a selected numbering system

Method for bit resynchronization of code-constrained sequences

Method and apparatus for encoding and decoding unordered error correcting codes

Coding method for skewed transition correction in parallel asynchronous communication systems

Increasing probability multi-stage network

Method and apparatus for writing and protecting against random and cluster errors in image blocks

Depth-2 threshold logic circuits for logic and arithmetic functions

Coding method for correction and detection of skewed transitions in parallel asynchronous communication systems

Coding method for skewed transition detection in parallel asynchronous communication system

Increasing probability multi-stage network

CALIFORNIA INST OF TECHN

Reliable array of distributed computing nodes

Error characterization and mitigation for 16nm MLC NAND flash memory under total ionizing dose effect

Geometric routing in wireless networks

Error characterization and mitigation for 16 nm MLC NAND flash memory under total ionizing dose effect

Precision-resolution constrained coding scheme

Rank-modulation rewriting codes for flash memories

Error characterization and mitigation for 16nm MLC NAND flash memory under total ionizing dose effect

NAND flash reliability with rank modulation

Communication efficient secret sharing

Synthesis of cyclic combinational circuits

Interval modulation coding

Flash memories using minimum push up, multi-cell and multi-permutation schemes for data storage

Flash memories using minimum push up, multi-cell and multi-permutation schemes for data storage

Joint rewriting and error correction in write-once memories

Rank-modulation rewriting codes for flash memories

Data transmission system and method

Secure raid schemes for distributed storage

Rewriting flash memories by message passing

Asymmetric error correction and flash-memory rewriting using polar codes

EMC CORP

Distributed traffic controller for network data

Dynamic network based storage with high availability

Distributed traffic controller for network data

RAINFINITY INC

Distributed server cluster for controlling network traffic

Distributed server cluster with graphical user interface

JIANG ANXIAO

Rank modulation for flash memories

Error correcting codes for rank modulation

CASSUTO YUVAL

Codes for limited magnitude asymmetric errors in flash memories

TEXAS A & M UNIV SYS

Storing information in a memory

TAMO ITZHAK

MDS array codes with optimal building