Inventor

SAUTER WOLFGANG

US174 patents

⚠️ This page may combine multiple inventors who share the name “SAUTER WOLFGANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAUTER WOLFGANG

IBM

Electrical interconnection structure formation

Conductive pillar shaped for solder confinement

Undercut-free BLM process for Pb-free and Pb-reduced C4

Undercut-free BLM process for Pb-free and Pb-reduced C4

Solder bumps in flip-chip technologies

Damascene patterning of barrier layer metal for C4 solder bumps

Chip dicing

Chip dicing

Probing pads in kerf area for wafer testing

Electrical interconnection structure formation

Design structure for final via designs for chip stress reduction

Post bump passivation for soft error protection

On-pad broadband matching network

Wirebond crack sensor for low-k die

Internally reinforced bond pads

Conductive pillar shaped for solder confinement

Structures to enable a full intermetallic interconnect

Nanowires for pillar interconnects

Conductive pillar shaped for solder confinement

Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip

Coplanar waveguide for stacked multi-chip systems

Substrate anchor structure and method

IC chip package having IC chip with overhang and/or BGA blocking underfill material flow and related methods

Structures and methods for improving solder bump connections in semiconductor devices

Substrate anchor structure and method

Current distribution structure and method

Final via structures for bond pad-solder ball interconnections

Sensor, method, and design structure for a low-k delamination sensor

Method for forming C4 connections on integrated circuit chips and the resulting devices

Wire and solder bond forming methods

Damascene patterning of barrier layer metal for C4 solder bumps

Dual-sided chip attached modules

Prevention of backside cracks in semiconductor chips or wafers using backside film or backside wet etch

Methods for forming co-planar wafer-scale chip packages

Chip dicing

Chip underfill in flip-chip technologies

Overcoming chip warping to enhance wetting of solder bumps and flip chip attaches in a flip chip package

Optimum padset for wire bonding RF technologies with high-Q inductors

Method of polishing C4 molybdenum masks to remove molybdenum peaks

DAUBENSPECK TIMOTHY H

Structure and method of making an offset-trench crackstop that forms an air gap adjacent to a passivated metal crackstop

Metal pad structure for thickness enhancement of polymer used in electrical interconnection of semiconductor die to semiconductor chip package substrate with solder bump

Ni plating of a BLM edge for Pb-free C4 undercut control

Structures and methods to improve lead-free C4 interconnect reliability

Underfill flow guide structures

Chip package solder interconnect formed by surface tension

Solder bump connections

ARVIN CHARLES L

Solder interconnect with non-wettable sidewall pillars and methods of manufacture

Undercut-repair of barrier layer metallurgy for solder bumps and methods thereof

MARVELL INT LTD

Multi-chip module (MCM) with chip-to-chip connection redundancy and method

HARVEY PAUL M

Method and apparatus to reduce impedance discontinuity in packages