Inventor
TEIG STEVEN
US318 patents
⚠️ This page may combine multiple inventors who share the name “TEIG STEVEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TABULA INC
24 patentsUS7342415B2Mar 11, 2008
Configurable IC with interconnect circuits that also perform storage operations
TABULA INC264 citations99
US7948266B2May 24, 2011
Non-sequentially configurable IC
TABULA INC64 citations98
US7532032B2May 12, 2009
Configurable circuits, IC's, and systems
TABULA INC71 citations98
US7530033B2May 5, 2009
Method and apparatus for decomposing functions in a configurable IC
TABULA INC61 citations98
US7521958B2Apr 21, 2009
Hybrid configurable circuit for a configurable IC
TABULA INC56 citations98
US7295037B2Nov 13, 2007
Configurable IC with routing circuits with offset connections
TABULA INC70 citations98
US8984464B1Mar 17, 2015
Detailed placement with search and repair
TABULA INC62 citations97
US7898291B2Mar 1, 2011
Operational time extension
TABULA INC36 citations96
US7788478B2Aug 31, 2010
Accessing multiple user states concurrently in a configurable IC
TABULA INC34 citations96
US7696780B2Apr 13, 2010
Runtime loading of configuration data in a configurable IC
TABULA INC39 citations96
US7667486B2Feb 23, 2010
Non-sequentially configurable IC
TABULA INC38 citations96
US7587698B1Sep 8, 2009
Operational time extension
TABULA INC50 citations96
US7576564B2Aug 18, 2009
Configurable IC with routing circuits with offset connections
TABULA INC45 citations96
US7548085B2Jun 16, 2009
Random access of user design states in a configurable IC
TABULA INC38 citations96
US7529992B1May 5, 2009
Configurable integrated circuit with error correcting circuitry
TABULA INC70 citations96
US7525344B2Apr 28, 2009
Configurable IC having a routing fabric with storage elements
TABULA INC29 citations96
US7512850B2Mar 31, 2009
Checkpointing user design states in a configurable IC
TABULA INC42 citations96
US7492186B2Feb 17, 2009
Runtime loading of configuration data in a configurable IC
TABULA INC41 citations96
US7428721B2Sep 23, 2008
Operational cycle assignment in a configurable IC
TABULA INC41 citations96
US7425841B2Sep 16, 2008
Configurable circuits, IC's, and systems
TABULA INC48 citations96
US7317331B2Jan 8, 2008
Reconfigurable IC that has sections running at different reconfiguration rates
TABULA INC45 citations96
US7259587B1Aug 21, 2007
Configurable IC's with configurable logic resources that have asymetric inputs and/or outputs
TABULA INC49 citations96
US7595655B2Sep 29, 2009
Retrieving data from a configurable IC
TABULA INC53 citations94
US7694265B2Apr 6, 2010
Operational cycle assignment in a configurable IC
TABULA INC19 citations93
CADENCE DESIGN SYSTEMS INC
17 patentsUS6526555B1Feb 25, 2003
Method for layout and manufacture of gridless non manhattan semiconductor integrated circuits using compaction
CADENCE DESIGN SYSTEMS INC104 citations99
US6516455B1Feb 4, 2003
Partitioning placement method using diagonal cutlines
CADENCE DESIGN SYSTEMS INC127 citations99
US7117468B1Oct 3, 2006
Layouts with routes with different spacings in different directions on the same layer, and method and apparatus for generating such layouts
CADENCE DESIGN SYSTEMS INC104 citations98
US6711727B1Mar 23, 2004
Method and arrangement for layout and manufacture of gridless nonManhattan semiconductor integrated circuits
CADENCE DESIGN SYSTEMS INC91 citations98
US7155440B1Dec 26, 2006
Hierarchical data processing
CADENCE DESIGN SYSTEMS INC69 citations97
US6701306B1Mar 2, 2004
Methods and apparatus for manipulating polygons in a multidimensional space
CADENCE DESIGN SYSTEMS INC78 citations97
US6625611B1Sep 23, 2003
Method and apparatus for representing multidimensional data
CADENCE DESIGN SYSTEMS INC86 citations97
US6907591B1Jun 14, 2005
Method and apparatus for performing extraction using a neural network
CADENCE DESIGN SYSTEMS INC62 citations96
US6898773B1May 24, 2005
Method and apparatus for producing multi-layer topological routes
CADENCE DESIGN SYSTEMS INC45 citations96
US6895567B1May 17, 2005
Method and arrangement for layout of gridless nonManhattan semiconductor integrated circuit designs
CADENCE DESIGN SYSTEMS INC43 citations96
US6769105B1Jul 27, 2004
Method and arrangement for layout and manufacture of gridded non manhattan semiconductor integrated circuits
CADENCE DESIGN SYSTEMS INC40 citations96
US6735748B1May 11, 2004
Method and apparatus for performing extraction using a model trained with bayesian inference
CADENCE DESIGN SYSTEMS INC53 citations96
US6687893B2Feb 3, 2004
Method and apparatus for pre-computing routes for multiple wiring models
CADENCE DESIGN SYSTEMS INC44 citations96
US6671864B2Dec 30, 2003
Method and apparatus for using a diagonal line to measure an attribute of a bounding box of a net
CADENCE DESIGN SYSTEMS INC39 citations96
US6651233B2Nov 18, 2003
Method and apparatus for measuring congestion in a partitioned region
CADENCE DESIGN SYSTEMS INC37 citations96
US7117470B1Oct 3, 2006
Method and system for distributing clock signals on non Manhattan semiconductor integrated circuits
CADENCE DESIGN SYSTEMS INC30 citations95
US6959304B1Oct 25, 2005
Method and apparatus for representing multidimensional data
CADENCE DESIGN SYSTEMS INC59 citations95
SCHMIT HERMAN
4 patentsUS7193440B1Mar 20, 2007
Configurable circuits, IC's, and systems
SCHMIT HERMAN125 citations99
US7109752B1Sep 19, 2006
Configurable circuits, IC's, and systems
SCHMIT HERMAN124 citations99
US7167025B1Jan 23, 2007
Non-sequentially configurable IC
SCHMIT HERMAN69 citations98
US7157933B1Jan 2, 2007
Configurable circuits, IC's, and systems
SCHMIT HERMAN79 citations98
HUTCHINGS BRAD
2 patentsROHE ANDRE
1 patentPERCEIVE CORP
1 patentTEIJIN LTD
1 patentShowing the top 50 of 318 patents by PatentIndex Score.