Inventor

LIN KAO-CHENG

TW50 patents

⚠️ This page may combine multiple inventors who share the name “LIN KAO-CHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIN KAO-CHENG

TAIWAN SEMICONDUCTOR MFG CO LTD

Static random access memory with a supplementary driver circuit and method of controlling the same

Dual port SRAM with dummy read recovery

Apparatus and method of three dimensional conductive lines

Layout design for manufacturing a memory cell

Semiconductor memory with respective power voltages for memory cells

Apparatus and method of three dimensional conductive lines

Apparatus and method of three dimensional conductive lines

Memory with bit line control

Three dimensional cross-access dual-port bit cell design

Scan synchronous-write-through testing architectures for a memory device

Scan synchronous-write-through testing architectures for a memory device

Multi-stage bit line pre-charge

Electronic circuits, memory devices, and methods for operating an electronic circuit

Reducing internal node loading in combination circuits

Static random access memory with a supplementary driver circuit and method of controlling the same

Reducing internal node loading in combination circuits

Static random access memory with a supplementary driver circuit and method of controlling the same

Reducing internal node loading in combination circuits

Semiconductor memory with respective power voltages for memory cells

Static random access memory with a supplementary driver circuit and method of controlling the same

Multi-port memory cell

Header circuit placement in memory device

Device and circuit with voltage suppression

Memory device and manufacturing method of the same

Header circuit placement in memory device

Header circuit placement in memory device

Sense amplifier layout for FinFET technology

Integrated circuit device and method

Memory device, method, layout, and system

Scan synchronous-write-through testing architectures for a memory device

Multi-stage bit line pre-charge

Multi-stage bit line pre-charge

Scan synchronous-write-through testing architectures for a memory device

Sense amplifier layout for FinFET technology

Sense amplifier layout for FinFET technology

Memory device

Shared power footer circuit

Apparatus and method of three dimensional conductive lines

Semiconductor memory with respective power voltages for plurality of memory cells

Multi-port memory cell

Variable-sized active regions for a semiconductor device and methods of making same

Integrated circuit, system and method of forming the same

Sense amplifier layout for FinFET technology

Static random access memory (SRAM) with recovery circuit for a write operation

TAIWAN SEMICONDUCTOR MFG

Static random access memory with assist circuit

Multi-port memory cell

YANG CHEN-LIN

Memory circuit

TAIWAN SEMICONDUCTOR MFG COMPANY LTD

Integrated circuit and method of forming the same

UNIV NAT SUN YAT SEN

Trench silicon-on-insulator (SOI) DRAM cell

LIN KAO-CHENG

Method and apparatus of electrical device characterization