Inventor
GHIASI ALI
US47 patents
⚠️ This page may combine multiple inventors who share the name “GHIASI ALI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
BROADCOM CORP
29 patentsUS7451362B2Nov 11, 2008
Method and system for onboard bit error rate (BER) estimation in a port bypass controller
BROADCOM CORP43 citations92
US7321612B2Jan 22, 2008
Bit stream conditioning circuit having adjustable PLL bandwidth
BROADCOM CORP31 citations92
US7317769B2Jan 8, 2008
Bit stream conditioning circuit having adjustable input sensitivity
BROADCOM CORP31 citations92
US7986622B2Jul 26, 2011
Method and system for physical layer aggregation
BROADCOM CORP28 citations91
US8014471B2Sep 6, 2011
Bit stream conditioning circuit having adjustable input sensitivity
BROADCOM CORP11 citations84
US7676158B2Mar 9, 2010
Method and system for optimum channel equalization from a SerDes to an optical module
BROADCOM CORP10 citations84
US7664170B2Feb 16, 2010
Bit stream linear equalizer with AGC loop
BROADCOM CORP10 citations84
US7961781B2Jun 14, 2011
Electronic dispersion compensation utilizing interleaved architecture and channel identification for assisting timing recovery
BROADCOM CORP8 citations83
US7206337B2Apr 17, 2007
Bit stream conditioning circuit having output pre-emphasis
BROADCOM CORP7 citations74
US9130851B2Sep 8, 2015
System and method for increasing input/output speeds in a network switch
BROADCOM CORP5 citations69
US7515629B2Apr 7, 2009
Conditioning circuit that spectrally shapes a serviced bit stream
BROADCOM CORP2 citations63
US7257154B2Aug 14, 2007
Multiple high-speed bit stream interface circuit
BROADCOM CORP1 citations63
US7765343B2Jul 27, 2010
Method and system for robust elastic FIFO (EFIFO) in a port bypass controller
BROADCOM CORP4 citations62
US7577171B2Aug 18, 2009
Source centered clock supporting quad 10 GBPS serial interface
BROADCOM CORP3 citations62
US7492783B2Feb 17, 2009
Method and system for LIPf7 origination detection and LIPf8 suppression in a port bypass controller
BROADCOM CORP3 citations62
US7443890B2Oct 28, 2008
Multi-stage multiplexing chip set having switchable forward/reverse clock relationship
BROADCOM CORP2 citations62
US7346082B2Mar 18, 2008
High-speed serial bit stream multiplexing and demultiplexing integrated circuits
BROADCOM CORP3 citations62
US7702010B2Apr 20, 2010
System for monitoring the quality of a communications channel with mirror receivers
BROADCOM CORP4 citations61
US7339986B2Mar 4, 2008
Method of monitoring the quality of a communications channel
BROADCOM CORP2 citations61
US7333537B2Feb 19, 2008
System for monitoring the quality of a communications channel with mirror receivers
BROADCOM CORP4 citations61
US9197368B2Nov 24, 2015
Inband management of ethernet links
BROADCOM CORP2 citations59
US7349450B2Mar 25, 2008
Multi-stage high speed bit stream demultiplexer chip set having switchable master/slave relationship
BROADCOM CORP4 citations56
US9143464B2Sep 22, 2015
Method and system for speed negotiation for twisted pair links using intelligent E-FIFO in fibre channel systems
BROADCOM CORP0 citations52
US9008105B2Apr 14, 2015
System and method for 10/40 gigabit ethernet multi-lane gearbox
BROADCOM CORP0 citations52
US9008127B2Apr 14, 2015
Method and system for speed negotiation for twisted pair links in fibre channel systems
BROADCOM CORP0 citations52
US7643543B2Jan 5, 2010
Multiple high-speed bit stream interface circuit
BROADCOM CORP0 citations52
US7313097B2Dec 25, 2007
Loop back testing structure for high-speed serial bit stream TX and RX chip set
BROADCOM CORP0 citations52
US8964907B2Feb 24, 2015
Multi-protocol communications receiver with shared analog front-end
BROADCOM CORP1 citations50
US9485199B2Nov 1, 2016
System and method for data flow identification and alignment in a 40/100 gigabit ethernet gearbox
BROADCOM CORP0 citations42
GHIASI ALI
7 patentsUS10866376B1Dec 15, 2020
Method and system for co-packaging photonics integrated circuit with an application specific integrated circuit
GHIASI ALI48 citations94
US8571070B2Oct 29, 2013
Method and system for speed negotiation for twisted pair links in fibre channel sytems
GHIASI ALI7 citations84
US8693885B2Apr 8, 2014
Method and system for optimum channel equalization from a SerDes to an optical module
GHIASI ALI4 citations73
US8873591B2Oct 28, 2014
System and method for bit-multiplexed data streams over multirate gigabit Ethernet
GHIASI ALI5 citations71
US8582437B2Nov 12, 2013
System and method for increasing input/output speeds in a network switch
GHIASI ALI2 citations58
US8396101B2Mar 12, 2013
Multiple high-speed bit stream interface circuit
GHIASI ALI0 citations52
US8306070B2Nov 6, 2012
Method and system for speed negotiation for twisted pair links using intelligent E-FIFO in fibre channel systems
GHIASI ALI0 citations52