Inventor

WISOR MICHAEL T

US28 patents

⚠️ This page may combine multiple inventors who share the name “WISOR MICHAEL T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WISOR MICHAEL T

ADVANCED MICRO DEVICES INC

Method an apparatus for encrypting and decrypting microprocessor serial numbers

Power management system distinguishing between primary and secondary system activity

System and method for reconfiguring configuration registers of a PCI bus device in response to a change in clock signal frequency

Method and apparatus for software access to a microprocessor serial number

Method and apparatus for upgrading the software lock of microprocessor

Power management control technique for timer tick activity within an interrupt driven computer system

Auto DRAM parity enable/disable mechanism

Power management unit including software configurable state register and time-out counters for protecting against misbehaved software

Disable technique employed during low battery conditions within a portable computer system

System and method for simulating a multiprocessor environment for testing a multiprocessing interrupt controller

System and method for providing microprocessor serialization using programmable fuses

Method and apparatus for serializing microprocessor identification numbers

System for receiving peripheral device capability information and selectively disabling corresponding processing unit function when the device failing to support such function

Computer system employing an enable line for selectively adjusting a peripheral bus clock frequency

Fail-safe communication abort mechanism for parallel ports with selectable NMI or parallel port interrupt

System and method for enabling and disabling a clock run function to control a peripheral bus clock signal

Non-volatile memory system having a programmably selectable boot code section size

Hardware-based system for enabling data transfers between a CPU and chip set logic of a computer system on both edges of bus clock signal

Method and apparatus for dynamically displaying and causing the execution of software diagnostic/test programs for the silicon validation of microprocessors

Bios memory and multimedia data storage combination

System and method for testing and debugging a multiprocessing interrupt controller

Hardware initialization method that is independent of boot code architecture

Computer system employing an improved real time clock alarm

Power management unit including a programmable index register for accessing configuration registers

Immediate system management interrupt source with associated reason register

System management interrupt source including a programmable counter and power management system employing the same

Method for testing the non-cacheable region functioning of a cache memory controller

SPANSION LLC

Non-volatile memory system having a programmably selectable boot code section size