Inventor

TERZIOGLU ESIN

US121 patents

⚠️ This page may combine multiple inventors who share the name “TERZIOGLU ESIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TERZIOGLU ESIN

BROADCOM CORP

Memory architecture with single-port cell and dual-port (read and write) functionality

Memory redundance circuit techniques

Memory module with hierarchical functionality

Asynchronously resettable decoder for a semiconductor memory

Sense amplifier with offset cancellation and charge-share limited swing drivers

Refresh techniques for memory data retention

Asynchronously-resettable decoder with redundancy

Sense amplifier with offset cancellation and charge-share limited swing drivers

Limited swing driver circuit

Synchronous global controller for enhanced pipelining

Synchronous global controller for enhanced pipelining

Very dense SRAM circuits

Synchronous controlled, self-timed local SRAM block

System and method for controlling logical value and integrity of data in memory systems

Block redundancy implementation in hierarchical rams

Operational amplifier for an active pixel sensor

Active pixel array with matching analog-to-digital converters for image processing

Efficent column redundancy techniques

Block redundancy implementation in heirarchical RAM&#39;S

Memory redundancy circuit techniques

Burn in system and method for improved memory reliability

Memory architecture with single-port cell and dual-port (read and write) functionality

Synchronous global controller for enhanced pipelining

Synchronous global controller for enhanced pipelining

Synchronous controlled, self-timed local SRAM block

Apparatus and method of image processing to avoid image saturation

Sense amplifier with offset cancellation and charge-share limited swing drivers

Hardware and software programmable fuses for memory repair

Circuit technique for high speed low power data transfer bus

Synchronous controlled, self-timed local SRAM block

Asynchronously-resettable decoder with redundancy

Synchronous controlled, self-timed local SRAM block

Hardware and software programmable fuses for memory repair

Sense amplifier with adaptive reference generation

QUALCOMM INC

Hybrid ternary content addressable memory

Non-volatile memory with split write and read bitlines

Shared-diffusion standard cell architecture

SOC design with critical technology pitch alignment

Split chip solution for die-to-die serdes

NOVELICS LLC

Single-poly non-volatile memory cell

One-time-programmable memory

Integrated circuits with reduced leakage current

Low-power CAM cell

DRAM density enhancements

TERZIOGLU ESIN

Operational amplifier for an active pixel sensor

Non-volatile memory with split write and read bitlines

Memory pre-decoder circuits employing pulse latch(es) for reducing memory access times, and related systems and methods

MENTOR GRAPHICS CORP

NOR-OR decoder

AFGHAHI MORTEZA CYRUS

Single-ended sense amplifier with sample-and-hold reference

NOVELIES LLC

Memory row and column redundancy

Block redundancy implementation in heirarchical RAM'S