Inventor
BOYNAPALLI VENUGOPAL
US32 patents
Patents
32 patentsUS9831272B2Nov 28, 2017
Metal oxide semiconductor cell device architecture with mixed diffusion break isolation trenches
QUALCOMM INC26 citations93
US9755618B1Sep 5, 2017
Low-area low clock-power flip-flop
QUALCOMM INC7 citations84
US10103626B1Oct 16, 2018
Digital power multiplexor
QUALCOMM INC9 citations83
US9230691B1Jan 5, 2016
Shared repair register for memory redundancy
QUALCOMM INC7 citations82
US11710733B2Jul 25, 2023
Vertical power grid standard cell architecture
QUALCOMM INC4 citations73
US9979381B1May 22, 2018
Semi-data gated flop with low clock power/low internal power with minimal area overhead
QUALCOMM INC5 citations73
US10777640B2Sep 15, 2020
Standard cell architecture for gate tie-off
QUALCOMM INC1 citations72
US10600866B2Mar 24, 2020
Standard cell architecture for gate tie-off
QUALCOMM INC2 citations72
US10236886B2Mar 19, 2019
Multiple via structure for high performance standard cells
QUALCOMM INC1 citations72
US10038429B1Jul 31, 2018
High-speed soft-edge sense-amplifier-based flip-flop
QUALCOMM INC6 citations72
US9990984B1Jun 5, 2018
Pulse-stretcher clock generator circuit for high speed memory subsystems
QUALCOMM INC2 citations71
US9960231B2May 1, 2018
Standard cell architecture for parasitic resistance reduction
QUALCOMM INC2 citations71
US9806717B2Oct 31, 2017
High-speed level-shifting multiplexer
QUALCOMM INC2 citations67
US9577639B1Feb 21, 2017
Source separated cell
QUALCOMM INC3 citations66
US12431877B2Sep 30, 2025
Hybrid flop tray including different fin size flip-flops
QUALCOMM INC0 citations62
US11237580B1Feb 1, 2022
Systems and methods providing leakage reduction for power gated domains
QUALCOMM INC0 citations62
US11133803B2Sep 28, 2021
Multiple via structure for high performance standard cells
QUALCOMM INC0 citations61
US10965289B2Mar 30, 2021
Metal oxide semiconductor device of an integrated circuit
QUALCOMM INC0 citations61
US10490543B2Nov 26, 2019
Placement methodology to remove filler
QUALCOMM INC1 citations60
US9071239B2Jun 30, 2015
Method and semiconductor apparatus for reducing power when transmitting data between devices in the semiconductor apparatus
QUALCOMM INC2 citations59
US9490813B2Nov 8, 2016
High-speed level-shifting multiplexer
QUALCOMM INC2 citations56
US12323142B2Jun 3, 2025
Integrated power management cells for gate all around technologies
QUALCOMM INC0 citations51
US11437379B2Sep 6, 2022
Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits
QUALCOMM INC0 citations51
US10784345B2Sep 22, 2020
Standard cell architecture for gate tie-off
QUALCOMM INC0 citations51
US9979394B2May 22, 2018
Pulse-generator
QUALCOMM INC1 citations51
US11361817B2Jun 14, 2022
Pseudo-triple-port SRAM bitcell architecture
QUALCOMM INC0 citations50
US12334143B2Jun 17, 2025
Power level comparator with switching input
QUALCOMM INC0 citations48
US11290109B1Mar 29, 2022
Multibit multi-height cell to improve pin accessibility
QUALCOMM INC0 citations48
US9189438B2Nov 17, 2015
Method and apparatus for dynamic power saving with flexible gating in a cross-bar architecture
QUALCOMM INC1 citations48
US10692808B2Jun 23, 2020
High performance cell design in a technology with high density metal routing
QUALCOMM INC0 citations37
US9081060B2Jul 14, 2015
Buffer testing for reconfigurable instruction cell arrays
QUALCOMM INC0 citations36
US9666301B2May 30, 2017
Scannable memories with robust clocking methodology to prevent inadvertent reads or writes
QUALCOMM INC0 citations34