Inventor
ZHANG KEVIN X
US34 patents
⚠️ This page may combine multiple inventors who share the name “ZHANG KEVIN X”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
29 patentsUS6038693AMar 14, 2000
Error correction scheme for an integrated L2 cache
INTEL CORP59 citations96
US6442089B1Aug 27, 2002
Multi-level, low voltage swing sensing scheme for high speed memory design
INTEL CORP33 citations93
US6292401B1Sep 18, 2001
Method and apparatus for global bitline multiplexing for a high-speed memory
INTEL CORP23 citations93
US6948079B2Sep 20, 2005
Method and apparatus for providing supply voltages for a processor
INTEL CORP19 citations92
US6518826B2Feb 11, 2003
Method and apparatus for dynamic leakage control
INTEL CORP36 citations92
US6198656B1Mar 6, 2001
Asymmetric memory cell for single-ended sensing
INTEL CORP37 citations92
US6026011AFeb 15, 2000
CMOS latch design with soft error immunity
INTEL CORP42 citations92
US6255861B1Jul 3, 2001
Hybrid low voltage swing sense amplifier
INTEL CORP16 citations84
US6622267B1Sep 16, 2003
Method and apparatus for detecting multi-hit errors in cache
INTEL CORP10 citations74
US6330182B1Dec 11, 2001
Method for evaluating soft error immunity of CMOS circuits
INTEL CORP10 citations74
US6204698B1Mar 20, 2001
Robust low voltage swing sense amplifier
INTEL CORP10 citations74
US6992405B2Jan 31, 2006
Dynamic voltage scaling scheme for an on-die voltage differentiator design
INTEL CORP9 citations73
US6621726B2Sep 16, 2003
Biasing technique for a high density SRAM
INTEL CORP7 citations73
US6483375B1Nov 19, 2002
Low power operation mechanism and method
INTEL CORP6 citations69
US6775181B2Aug 10, 2004
Biasing technique for a high density SRAM
INTEL CORP7 citations66
US7089360B1Aug 8, 2006
Shared cache wordline decoder for redundant and regular addresses
INTEL CORP3 citations63
US6862225B2Mar 1, 2005
Buffer for a split cache line access
INTEL CORP2 citations63
US6816554B1Nov 9, 2004
Communication bus for low voltage swing data signals
INTEL CORP3 citations63
US6507531B1Jan 14, 2003
Cache column multiplexing using redundant form addresses
INTEL CORP4 citations63
US6456121B2Sep 24, 2002
Sense amplifier for integrated circuits using PMOS transistors
INTEL CORP3 citations63
US6198684B1Mar 6, 2001
Word line decoder for dual-port cache memory
INTEL CORP2 citations63
US6087849AJul 11, 2000
Soft error immunity in CMOS circuits with large shared diffusion areas
INTEL CORP5 citations63
US6982500B2Jan 3, 2006
Power-down scheme for an on-die voltage differentiator design
INTEL CORP2 citations62
US6407589B1Jun 18, 2002
Device for current sensing in an amplifier with PMOS voltage conversion
INTEL CORP6 citations62
US6650171B2Nov 18, 2003
Low power operation mechanism and method
INTEL CORP3 citations58
US7337372B2Feb 26, 2008
Method and apparatus for detecting multi-hit errors in a cache
INTEL CORP0 citations52
US6778444B1Aug 17, 2004
Buffer for a split cache line access
INTEL CORP0 citations52
US9123724B2Sep 1, 2015
Methods of forming secured metal gate antifuse structures
INTEL CORP1 citations49
US9013941B2Apr 21, 2015
DRAM with pulse sense amp
INTEL CORP1 citations47