Inventor

VEGA REINALDO A

US86 patents

⚠️ This page may combine multiple inventors who share the name “VEGA REINALDO A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VEGA REINALDO A

IBM

Method of fabricating vertical field effect transistors with protective fin liner during bottom spacer recess etch

Vertical FETs with variable bottom spacer recess

Vertical field effect transistor with subway etch replacement metal gate

Vertical FETs with variable bottom spacer recess

Selective dielectric spacer deposition for exposing sidewalls of a finFET

Silicide contacts having different shapes on regions of a semiconductor device

Vertical FETS with variable bottom spacer recess

Nanosheet MOSFET with partial release and source/drain epitaxy

Tunnel transistors with abrupt junctions

Nanosheet field effect transistors with partial inside spacers

Method of fabricating vertical field effect transistors with protective fin liner during bottom spacer recess ETCH

Vertical fin field effect transistor with air gap spacers

Vertical field effect transistors having epitaxial fin channel with spacers below gate structure

Self aligned replacement metal source/drain finFET

Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation

Coaxial carbon nanotube capacitor for eDRAM

Fin end spacer for preventing merger of raised active regions

Multi-composition gate dielectric field effect transistors

Fin field effect transistors having heteroepitaxial channels

FinFET device formation

Two-step silicide formation

Nanosheet field effect transistors with partial inside spacers

Vertical FET devices with multiple channel lengths

Self aligned replacement metal source/drain finFET

Multiple-threshold nanosheet transistors

Vertical fin field effect transistor with air gap spacers

Vertical fin field effect transistor with air gap spacers

Vertical field effect transistors with protective fin liner during bottom spacer recess etch

Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation

FinFET device formation

Two-step silicide formation

Vertical FETS with variable bottom spacer recess

Partial spacer for increasing self aligned contact process margins

Semiconductor fin isolation by a well trapping fin portion

Vertical fin field effect transistor with air gap spacers

Vertical FET devices with multiple channel lengths

Forming MOSFET structures with work function modification

Selective dielectric spacer deposition for exposing sidewalls of a finFET

Trench isolation structure

Vertical fin field effect transistor with air gap spacers

Patterned sidewall smoothing using a pre-smoothed inverted tone pattern

GLOBALFOUNDRIES INC

Forming fins of different semiconductor materials on the same substrate

Semiconductor devices with graphene nanoribbons

Fin-type field-effect transistors with strained channels

VEGA REINALDO A

Semiconductor fin on local oxide

Method of fabricating tunnel transistors with abrupt junctions

TESSERA INC

Nanosheet field effect transistors with partial inside spacers

Self aligned replacement metal source/drain finFET

TESSERA LLC

Self aligned replacement metal source/drain FINFET

AQUILINO MICHAEL V

Trench isolation structure