Inventor · disambiguated record
Raul Oteyza
Also filed as: OTEYZA RAUL · OTEYZA RAUL BERSAMIN
8 granted patents·59 citations·filing 1999–2017
84Inventor score
Top patents by PatentIndex Score
8 records- 0175US6647081B2Phase-locked loop (PLL) circuit for selectively correcting clock skew in different modesEMULEX CORP·Filed 2002·Granted Nov 11, 2003·20 cites·10 claims
- 0272US9588839B1Methods and systems for using shared logic at network devicesQLOGIC CORP·Filed 2015·Granted Mar 7, 2017·2 cites·20 claims
- 0364US6728861B1Queuing fibre channel receive framesEMULEX CORP·Filed 2003·Granted Apr 27, 2004·9 cites·21 claims
- 0460US7227921B2Phase-locked loop (PLL) circuit for selectively correcting clock skew in different modesEMULEX DESIGN & MFG CORP·Filed 2003·Granted Jun 5, 2007·7 cites·11 claims
- 0557US7403203B2Stacking series of non-power-of-two frame buffers in a memory arrayEMULEX DESIGN & MFG CORP·Filed 2005·Granted Jul 22, 2008·1 cites·18 claims
- 0648US10020929B1Methods and systems for data alignment in network devicesCAVIUM INC·Filed 2017·Granted Jul 10, 2018·0 cites·20 claims
- 0745US6459701B1Variable access fairness in a fibre channel arbitrated loopEMULEX CORP·Filed 1999·Granted Oct 1, 2002·20 cites·18 claims
- 0836US8111696B2Method to improve the performance of a computer networkNGUYEN VUONG CAO·Filed 2008·Granted Feb 7, 2012·0 cites·11 claims
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