Inventor
HOSSAIN RAZAK
US22 patents
⚠️ This page may combine multiple inventors who share the name “HOSSAIN RAZAK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ST MICROELECTRONICS INC
11 patentsUS7571402B2Aug 4, 2009
Scan chain modification for reduced leakage
ST MICROELECTRONICS INC11 citations83
US6911845B2Jun 28, 2005
Pulse triggered static flip-flop having scan test
ST MICROELECTRONICS INC18 citations82
US7002374B2Feb 21, 2006
Domino logic compatible scannable flip-flop
ST MICROELECTRONICS INC11 citations79
US7337419B2Feb 26, 2008
Crosstalk noise reduction circuit and method
ST MICROELECTRONICS INC5 citations62
US6729168B2May 4, 2004
Circuit for determining the number of logical one values on a data bus
ST MICROELECTRONICS INC6 citations62
US6665691B2Dec 16, 2003
Circuit for detecting numbers equal to a power of two on a data bus
ST MICROELECTRONICS INC4 citations62
US7301372B2Nov 27, 2007
Domino logic compatible scannable flip-flop
ST MICROELECTRONICS INC3 citations57
US7254796B2Aug 7, 2007
Method for synthesizing domino logic circuits cross reference to related patent application using partition
ST MICROELECTRONICS INC3 citations57
US6954909B2Oct 11, 2005
Method for synthesizing domino logic circuits
ST MICROELECTRONICS INC3 citations57
US9032354B2May 12, 2015
Scan chain modification for reduced leakage
ST MICROELECTRONICS INC0 citations51
US6820109B2Nov 16, 2004
System and method for predictive comparator following addition
ST MICROELECTRONICS INC0 citations41
MENTOR GRAPHICS CORP
4 patentsUS6148316ANov 14, 2000
Floating point unit equipped also to perform integer addition as well as floating point to integer conversion
MENTOR GRAPHICS CORP38 citations89
US6134576AOct 17, 2000
Parallel adder with independent odd and even sum bit generation cells
MENTOR GRAPHICS CORP7 citations72
US6195672B1Feb 27, 2001
Saturation detection in floating point to integer conversions
MENTOR GRAPHICS CORP7 citations70
US6148315ANov 14, 2000
Floating point unit having a unified adder-shifter design
MENTOR GRAPHICS CORP0 citations50
QUALCOMM INC
4 patentsUS11411569B2Aug 9, 2022
Calibration of sampling-based multiplying delay-locked loop (MDLL)
QUALCOMM INC3 citations72
US12531564B2Jan 20, 2026
Synchronizing multiple phase-locked loop circuits
QUALCOMM INC0 citations62
US11595028B2Feb 28, 2023
Frequency doubler with duty cycle correction
QUALCOMM INC1 citations61
US12512958B2Dec 30, 2025
Phase tracking and correction architecture
QUALCOMM INC0 citations59