Inventor

HOLMES STEVEN JOHN

US52 patents

⚠️ This page may combine multiple inventors who share the name “HOLMES STEVEN JOHN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOLMES STEVEN JOHN

IBM

Method for forming quadruple density sidewall image transfer (SIT) structures

FET with T-shaped gate

Self-isolated and self-aligned 4F-square vertical fet-trench dram cells

Trench storage dram cell including a step transfer device

Vertical nanotube semiconductor device structures and methods of forming the same

Micro-electro-mechanical valves and pumps and methods of fabricating same

Memory devices using carbon nanotube (CNT) technologies

Method of forming fet with T-shaped gate

Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes

Strained semiconductor device structures

Selective synthesis of semiconducting carbon nanotubes

Methods of making a trench storage DRAM cell including a step transfer device

Chemical trim of photoresist lines by means of a tuned overcoat material

Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage

Method of making a rim-type phase-shift mask and mask manufactured thereby

Methods and structures for promoting stable synthesis of carbon nanotubes

Method of forming FinFET gates without long etches

Vertical carbon nanotube field effect transistors and arrays

Micro-electro-mechanical valves and pumps

Shallow trench isolation fill by liquid phase deposition of SiO2

Vertical DRAM having metallic node conductor

Method for improving visibility of alignment targets in semiconductor processing

Method for making integrated circuit chip utilizing oriented carbon nanotube conductive layers

Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage

Integrated circuit chip utilizing oriented carbon nanotube conductive layers

Method for improving visibility of alignment target in semiconductor processing

Non-volatile switching and memory devices using vertical nanotubes

Methods of forming low-k dielectric layers containing carbon nanostructures

Electric fuses using CNTs (carbon nanotubes)

Memory devices using carbon nanotube (CNT) technologies

Methods of forming alternating phase shift masks having improved phase-shift tolerance

Passive electrically testable acceleration and voltage measurement devices

Hybrid substrates and methods for forming such hybrid substrates

Removable passivating polyimide coating and methods of use

Method of temporarily bonding two surfaces

Methods of fabricating vertical carbon nanotube field effect transistors for arrangement in arrays and field effect transistors and arrays formed thereby

Method for fabricating an electrical connect above an integrated circuit

Metal-oxide-semiconductor device structures with tailored dopant depth profiles

Method of making integrated circuit chip utilizing oriented carbon nanotube conductive layers

Methods for fabricating a metal-oxide-semiconductor device structure

Methods and structures for promoting stable synthesis of carbon nanotubes

Integrated circuit chip utilizing oriented carbon nanotube conductive layers

Passive electrically testable acceleration and voltage measurement devices

Shallow trench isolation fill by liquid phase deposition of SiO2

Immersion lithography contamination gettering layer

Layer patterning using double exposure processes in a single photoresist layer

Design structure incorporating a hybrid substrate

(unassigned)

Method of forming self-isolated and self-aligned 4F-square vertical FET-trench DRAM cells

AUDIOTEL INTERNAT LTD

Non-linear junction detector

BURNS SEAN DAVID

Chemical trim of photoresist lines by means of a tuned overcoat