Inventor
LAOR MICHAEL
IL20 patents
⚠️ This page may combine multiple inventors who share the name “LAOR MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CISCO TECH IND
9 patentsUS6977930B1Dec 20, 2005
Pipelined packet switching and queuing architecture
CISCO TECH IND193 citations99
US6813243B1Nov 2, 2004
High-speed hardware implementation of red congestion control algorithm
CISCO TECH IND142 citations99
US6778546B1Aug 17, 2004
High-speed hardware implementation of MDRR algorithm over a large number of queues
CISCO TECH IND169 citations99
US6721316B1Apr 13, 2004
Flexible engine and data structure for packet header processing
CISCO TECH IND207 citations99
US6731644B1May 4, 2004
Flexible DMA engine for packet header modification
CISCO TECH IND99 citations98
US6147996ANov 14, 2000
Pipelined multiple issue packet switch
CISCO TECH IND124 citations98
US6980552B1Dec 27, 2005
Pipelined packet switching and queuing architecture
CISCO TECH IND196 citations97
US6831923B1Dec 14, 2004
Pipelined multiple issue packet switch
CISCO TECH IND103 citations97
US6424649B1Jul 23, 2002
Synchronous pipelined switch using serial transmission
CISCO TECH IND35 citations92
CISCO TECH INC
6 patentsUS7643486B2Jan 5, 2010
Pipelined packet switching and queuing architecture
CISCO TECH INC86 citations97
US8018937B2Sep 13, 2011
Pipelined packet switching and queuing architecture
CISCO TECH INC21 citations92
US7675926B2Mar 9, 2010
Hierarchical QoS behavioral model
CISCO TECH INC35 citations92
US7554907B1Jun 30, 2009
High-speed hardware implementation of RED congestion control algorithm
CISCO TECH INC24 citations92
US7304999B2Dec 4, 2007
Methods and apparatus for processing packets including distributing packets across multiple packet processing engines and gathering the processed packets from the processing engines
CISCO TECH INC27 citations92
US7286525B1Oct 23, 2007
Synchronous pipelined switch using serial transmission
CISCO TECH INC10 citations84