Inventor

MITRAN MARCEL

CA83 patents

⚠️ This page may combine multiple inventors who share the name “MITRAN MARCEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MITRAN MARCEL

IBM

Controlling operation of a run-time instrumentation facility from a lesser-privileged state

Conditional transaction end instruction

Defining memory indifferent trace handles

Conditional transaction end instruction

Conditional instruction end operation

Transaction begin/end instructions

Conditional transaction end instruction

Transaction abort instruction specifying a reason for abort

Transaction abort instruction specifying a reason for abort

Conditional instruction end operation

Conditional instruction end operation

Conditional transaction end instruction

Page mapped spatially aware emulation of computer instruction set

Transaction diagnostic block

Efficient code cache management in presence of infrequently used complied code fragments

Load logical and shift guarded instruction

Conditional instruction end operation

Identifying processor attributes based on detecting a guarded storage event

Compare and delay instructions

Compare and delay instructions

Run-time instrumentation reporting

Self initialized host cell spatially aware emulation of a computer instruction set

Transactional lock elision with delayed lock checking

Transaction begin/end instructions

Conditional transaction end instruction

Conditional instruction end operation

Compare and delay instructions

Transactional lock elision with delayed lock checking

Transaction abort instruction

Transaction begin/end instructions

Transactional lock elision with delayed lock checking

Convert from zoned format to decimal floating point format

Load pair disjoint facility and instruction therefor

Identifying processor attributes based on detecting a guarded storage event

BOHIZIC THEODORE J

Page mapped spatially aware emulation of a computer instruction set

Host cell spatially aware emulation of a guest wild branch

Self initialized host cell spatially aware emulation of a computer instruction set

Executing atomic store disjoint instructions

GREINER DAN F

Transaction diagnostic block

High-word facility for extending the number of general purpose registers available to instructions

Program interruption filtering in transactional execution

MITRAN MARCEL

Performance improvements for nested virtual machines

Eliminating redundant operations for common properties using shared real registers

Controlling tracing within compiled code

AMARAL JOSE NELSON

Mining sequential patterns in weighted directed graphs

Mining sequential patterns in weighted directed graphs

CARLOUGH STEVEN R

Convert from zoned format to decimal floating point format

Convert to zoned format from decimal floating point format

JACOBI CHRISTIAN

Load pair disjoint facility and instruction therefore

BOGSANYL FRANCIS

Accelerated execution for emulated environments