Inventor

LIAO CHIH-CHIN

TW54 patents

⚠️ This page may combine multiple inventors who share the name “LIAO CHIH-CHIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIAO CHIH-CHIN

SANDISK CORP

Stacked, interconnected semiconductor packages

Die package with asymmetric leadframe connection

Printed circuit board with coextensive electrical connectors and contact pad areas

Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages

Substrate warpage control and continuous electrical enhancement

Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging

High density three dimensional semiconductor die package

Padless substrate for surface mounted components

Semiconductor package having through holes for molding back side of package

Rounded contact fingers on substrate/PCB for crack prevention

Method of minimizing kerf width on a semiconductor substrate panel

Hidden plating traces

Method of fabricating a semiconductor package having through holes for molding back side of package

Methods of forming a single layer substrate for high capacity memory cards

SILICONWARE PRECISION INDUSTRIES CO LTD

Semiconductor package

Method of fabricating plated circuit lines over ball grid array substrate

Chip package capable of reducing moisture penetration

Semiconductor device and fabrication method of the same

Ball grid array package with interdigitated power ring and ground ring

Method for identifying defective elements in array molding of semiconductor packaging

Semiconductor package

Chip package capable of reducing moisture penetration

Integrated-circuit package with a quick-to-count finger layout design on substrate

Multi-chip packaging having non-sticking test structure

Substrate and fabrication method of the same

WESTERN DIGITAL TECH INC

Semiconductor device including optional pad interconnect

Printed circuit board trace for galvanic effect reduction

Semiconductor device including dummy pull-down wire bonds

Substrate bonding pad having a multi-surface trace interface

Side contact pads for high-speed memory card

TAKIAR HEM

Method of fabricating stacked semiconductor package with localized cavities for wire bonding

Stacked semiconductor package with localized cavities for wire bonding

Hidden plating traces

Hidden plating traces

Substrate panel with plating bar structured to allow minimum kerf width

LIAO CHIH-CHIN

Semiconductor device with die stack arrangement including staggered die and efficient wire bonding

Corrugated die edge for stacked die semiconductor package

Printed circuit board with coextensive electrical connectors and contact pad areas

Two-sided substrate lead connection for minimizing kerf width on a semiconductor substrate panel

SANDISK TECHNOLOGIES INC

Stacked, interconnected semiconductor package

Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging

Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging

Printed circuit board with coextensive electrical connectors and contact pad areas

SANDISK TECHNOLOGIES LLC

Wire bonded wide I/O semiconductor device

Wire bonded wide I/O semiconductor device

LEE MING HSUN

Die package with asymmetric leadframe connection

SANDISK SEMICONDUCTOR SHANGHAI CO LTD

Heterogeneous fan-out structures for memory devices

CHIU CHIN-TIEN

Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging

SANDISK INFORMATION TECH SHANGHAI CO LTD

Semiconductor device including control switches to reduce pin capacitance

UPADHYAYULA SURESH KUMAR

Radiation-shielded semiconductor device