Inventor
HOOVER RUSSELL DEAN
US32 patents
⚠️ This page may combine multiple inventors who share the name “HOOVER RUSSELL DEAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
18 patentsUS6557069B1Apr 29, 2003
Processor-memory bus architecture for supporting multiple processors
IBM169 citations99
US6526469B1Feb 25, 2003
Bus architecture employing varying width uni-directional command bus
IBM198 citations99
US8022950B2Sep 20, 2011
Stochastic culling of rays with increased depth of recursion
IBM134 citations98
US6247100B1Jun 12, 2001
Method and system for transmitting address commands in a multiprocessor system
IBM120 citations98
US5805837ASep 8, 1998
Method for optimizing reissue commands in master-slave processing systems
IBM96 citations98
US6088768AJul 11, 2000
Method and system for maintaining cache coherence in a multiprocessor-multicache environment having unordered communication
IBM48 citations93
US5761721AJun 2, 1998
Method and system for cache coherence despite unordered interconnect transport
IBM67 citations93
US7818503B2Oct 19, 2010
Method and apparatus for memory utilization
IBM17 citations92
US6006255ADec 21, 1999
Networked computer system and method of communicating using multiple request packet classes to prevent deadlock
IBM30 citations92
US7996621B2Aug 9, 2011
Data cache invalidate with data dependent expiration using a step value
IBM8 citations84
US7852336B2Dec 14, 2010
Dynamic determination of optimal spatial index mapping to processor thread resources
IBM11 citations84
US7836258B2Nov 16, 2010
Dynamic data cache invalidate with data dependent expiration
IBM8 citations84
US7752413B2Jul 6, 2010
Method and apparatus for communicating between threads
IBM11 citations84
US7669013B2Feb 23, 2010
Directory for multi-node coherent bus
IBM9 citations84
US6260090B1Jul 10, 2001
Circuit arrangement and method incorporating data buffer with priority-based data storage
IBM16 citations82
US7788452B2Aug 31, 2010
Method and apparatus for tracking cached addresses for maintaining cache coherency in a computer system having multiple caches
IBM9 citations79
US7725660B2May 25, 2010
Directory for multi-node coherent bus
IBM1 citations52
US7013375B2Mar 14, 2006
Configurable directory allocation
IBM0 citations52
BROWN JEFFREY DOUGLAS
7 patentsUS8139060B2Mar 20, 2012
Ray tracing image processing system
BROWN JEFFREY DOUGLAS140 citations97
US8085267B2Dec 27, 2011
Stochastic addition of rays in a ray tracing image processing system
BROWN JEFFREY DOUGLAS138 citations97
US8248402B2Aug 21, 2012
Adaptive ray data reorder for optimized ray temporal locality
BROWN JEFFREY DOUGLAS7 citations84
US8284195B2Oct 9, 2012
Cooperative utilization of spatial indices between application and rendering hardware
BROWN JEFFREY DOUGLAS6 citations73
US8259131B2Sep 4, 2012
Adaptive sub-sampling for reduction in issued rays
BROWN JEFFREY DOUGLAS4 citations62
US8259130B2Sep 4, 2012
Color buffer contrast threshold for adaptive anti-aliasing
BROWN JEFFREY DOUGLAS1 citations52
US9041713B2May 26, 2015
Dynamic spatial index remapping for optimal aggregate performance
BROWN JEFFREY DOUGLAS0 citations41
BARTLEY GERALD K
5 patentsUS8736068B2May 27, 2014
Hybrid bonding techniques for multi-layer semiconductor stacks
BARTLEY GERALD K215 citations98
US9495498B2Nov 15, 2016
Universal inter-layer interconnect for multi-layer semiconductor stacks
BARTLEY GERALD K19 citations91
US8445918B2May 21, 2013
Thermal enhancement for multi-layer semiconductor stacks
BARTLEY GERALD K17 citations83
US8293578B2Oct 23, 2012
Hybrid bonding techniques for multi-layer semiconductor stacks
BARTLEY GERALD K11 citations83
US8330489B2Dec 11, 2012
Universal inter-layer interconnect for multi-layer semiconductor stacks
BARTLEY GERALD K4 citations61