Inventor

HO YUEH-SE

US110 patents

⚠️ This page may combine multiple inventors who share the name “HO YUEH-SE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HO YUEH-SE

ALPHA & OMEGA SEMICONDUCTOR

Power semiconductor package

High speed switching MOSFETS using multi-parallel die packages with/without special leadframes

Embedded package and method thereof

Wafer level chip scale package and process of manufacture

Standing chip scale package

Wafer level chip scale package and process of manufacture

Vertical packaged IC device modules with interconnected 3D laminates directly contacts wafer backside

Integrated circuit package for semiconductor devices having a reduced leadframe pad and an increased bonding area

Power semiconductor package device having locking mechanism, and preparation method thereof

Inverted J-lead for power devices

Method of fabricating a semiconductor device employing electroless plating

Termination structure for gallium nitride Schottky diode

Wafer level chip scale package

SILICONIX INC

Surface mount and flip chip technology with diamond film passivation for total integated circuit isolation

Surface mount and flip chip technology for total integrated circuit isolation

Surface mount and flip chip technology for total integrated circuit isolation

Trenched DMOS transistor fabrication having thick termination region oxide

Trenched DMOS transistor having thick field oxide in termination region

Trenched DMOS transistor fabrication using six masks

Vertical structure for semiconductor wafer-level chip scale packages

IC chip package with directly connected leads

Semiconductor die package including cup-shaped leadframe

Trenched DMOS transistor with channel block at cell trench corners

XUE YAN XUN

Wafer level package structure and the fabrication method thereof

Packaging method of molded wafer level chip scale package (WLCSP)

Packaging method of molded wafer level chip scale package (WLCSP)

Power device with bottom source electrode

Semiconductor package of a flipped MOSFET and its manufacturing method

Stacked power semiconductor device using dual lead frame and manufacturing method

Top exposed package and assembly method

Semiconductor device employing aluminum alloy lead-frame with anodized aluminum

VISHAY INTERTECHNOLOGY INC

Chip scale surface mount package for semiconductor device and process of fabricating the same

Chip scale surface mount packages for semiconductor device and process of fabricating the same

Process of fabricating a chip scale surface mount package for semiconductor device

Chip scale surface mount package for semiconductor device and process of fabricating the same

Chip scale surface mount package for semiconductor device and process of fabricating the same

HO YUEH-SE

Combined packaged power semiconductor device

Stacked dual-chip packaging structure and preparation method thereof

Combined packaged power semiconductor device

YILMAZ HAMZA

Stacked dual chip package and method of fabrication

Stacked multi-chip bottom source semiconductor device and preparation method thereof

SUN MING

Vertically packaged MOSFET and IC power devices as integrated module using 3D interconnected laminates

Methods and configuration for manufacturing flip chip contact (FCC) power package

LU JUN

Multi-layer lead frame package and method of fabrication

VISHAY SILICONIX

Chip scale surface mount package for semiconductor device and process of fabricating the same

(unassigned)

Integrated circuit package for semiconductor devices with improved electric resistance and inductance

LUO LEESHAWN

Integrated circuit package for semiconductor devices with improved electric resistance and inductance

MICROELECTRONICS CENTER OF NOR

Shared current loop, multiple field apparatus and process for plasma processing

ALPHA & OMEGA SEMICONDUCTOR INT LP

Method of making reverse conducting insulated gate bipolar transistor

BHALLA ANUP

Methods for fabricating anode shorted field stop insulated gate bipolar transistor