P

Inventor

STRICKER ANDREAS D

US43 patents
⚠️ This page may combine multiple inventors who share the name “STRICKER ANDREAS D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

27 patents
US7002221B2Feb 21, 2006

Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same

IBM17 citations93
US7888745B2Feb 15, 2011

Bipolar transistor with dual shallow trench isolation and low base resistance

IBM21 citations92
US6965133B2Nov 15, 2005

Method of base formation in a BiCMOS process

IBM16 citations92
US6906401B2Jun 14, 2005

Method to fabricate high-performance NPN transistors in a BiCMOS process

IBM19 citations92
US6809024B1Oct 26, 2004

Method to fabricate high-performance NPN transistors in a BiCMOS process

IBM24 citations92
US8908334B1Dec 9, 2014

Electrostatic discharge protection for a magnetoresistive sensor

IBM9 citations84
US7932541B2Apr 26, 2011

High performance collector-up bipolar transistor

IBM13 citations84
US7253096B2Aug 7, 2007

Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same

IBM11 citations84
US7180157B2Feb 20, 2007

Bipolar transistor with a very narrow emitter feature

IBM12 citations84
US7390721B2Jun 24, 2008

Methods of base formation in a BiCMOS process

IBM6 citations74
US7170083B2Jan 30, 2007

Bipolar transistor with collector having an epitaxial Si:C region

IBM9 citations74
US7136268B2Nov 14, 2006

Tunable ESD trigger and power clamp circuit

IBM9 citations74
US6858485B2Feb 22, 2005

Method for creation of a very narrow emitter feature

IBM8 citations74
US6844225B2Jan 18, 2005

Self-aligned mask formed utilizing differential oxidation rates of materials

IBM5 citations74
US10003191B2Jun 19, 2018

Space efficient and power spike resistant ESD power clamp with digitally timed latch

IBM2 citations73
US7696034B2Apr 13, 2010

Methods of base formation in a BiCOMS process

IBM6 citations73
US9978743B1May 22, 2018

Voltage balanced stacked clamp

IBM3 citations72
US7442595B2Oct 28, 2008

Bipolar transistor with collector having an epitaxial Si:C region

IBM3 citations63
US7288827B2Oct 30, 2007

Self-aligned mask formed utilizing differential oxidation rates of materials

IBM3 citations63
US10770892B2Sep 8, 2020

Space efficient and power spike resistant ESD power clamp with digitally timed latch

IBM1 citations62
US9601139B2Mar 21, 2017

Electrostatic discharge protection for a magnetoresistive sensor

IBM0 citations52
US9279862B2Mar 8, 2016

Electrostatic discharge protection for a magnetoresistive sensor

IBM0 citations52
US8946799B2Feb 3, 2015

Silicon controlled rectifier with stress-enhanced adjustable trigger voltage

IBM1 citations52
US7791105B2Sep 7, 2010

Device structures for a high voltage junction field effect transistor manufactured using a hybrid orientation technology wafer and design structures for a high voltage integrated circuit

IBM0 citations52
US10170460B2Jan 1, 2019

Voltage balanced stacked clamp

IBM0 citations51
US9660114B2May 23, 2017

Temperature stabilization of an on-chip temperature-sensitive element

IBM0 citations42
US7005686B1Feb 28, 2006

Mixed voltage tolerant electrostatic discharge protection silicon controlled rectifier with enhanced turn-on time

IBM0 citations39

GLOBALFOUNDRIES US INC

10 patents

GLOBALFOUNDRIES INC

3 patents

CAMILLO-CASTILLO RENATA

1 patent

MARVELL ASIA PTE LTD

1 patent

CAMILLO-CASTILLO RENATA A

1 patent