Inventor

VAN NORSTRAND JR ALBERT J

US31 patents

⚠️ This page may combine multiple inventors who share the name “VAN NORSTRAND JR ALBERT J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VAN NORSTRAND JR ALBERT J

IBM

Redistribution of architected states for a processor register file

Hardware based isolation for secure execution of virtual machines

Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline

Handling unaligned load operations in a multi-slice computer processor

Handling unaligned load operations in a multi-slice computer processor

Managing a divided load reorder queue

Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock condition

Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline

Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction

Handling unaligned load operations in a multi-slice computer processor

Compaction of architected registers in a simultaneous multithreading processor

Handling unaligned load operations in a multi-slice computer processor

Multi-level history buffer for transaction memory in a microprocessor

Asynchronous flush and restore of distributed history buffer

Techniques for reducing power requirements of an integrated circuit

Method and system for nonsequential execution of intermixed scalar and vector instructions in a data processing system utilizing a finish instruction array

Issue queue snooping for asynchronous flush and restore of distributed history buffer

Handling unaligned load operations in a multi-slice computer processor

Prioritized instructions in an instruction completion table of a simultaneous multithreading processor

Variable latency flush filtering

Managing an effective address table in a multi-slice processor

Managing an effective address table in a multi-slice processor

Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction

Identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor

Techniques for predicting a target address of an indirect branch instruction

Most favored branch issue

Blocking instruction fetching in a computer processor

Thread migration using a microcode engine of a multi-slice processor

DOING RICHARD W

Tracking effective addresses in an out-of-order processor

GLOBALFOUNDRIES INC

Virtual machine backup

ABERNATHY CHRISTOPHER M

Issue unit for placing a processor into a gradual slow mode of operation